CMSC 411CMSC 411Computer Systems ArchitectureLecture 16VirtualMemoryVirtual MemoryAlan Sussmanl@ d [email protected]• Homework #4 due in 1 week, April 14•Exam #2 pushed back to April 21•Exam #2 pushed back to April 21• Cache simulator project posted, due May 1– CSIC Linuxlab account info handed out today• Start reading Ch. 6 (not 6.5)• 400 level lecture series today and tomorrow, CSIC 2117 at 5PM, sponsored by AWCpyCMSC 411 - 16 (some from Patterson, Sussman, others)2Two-Level Page TablesEach process needs its own address space!Two-level Page Tables31 12 11 0212232 bit virtual addressP1 index P2 index Page OffsetTop-level tablewiredin main memoryTop-level table wiredin main memorySubset of 1024 second-level tables in main memory; rest are on disk or ll t dCMSC 411 - 16 (some from Patterson, Sussman, others)3unallocated Choosing page size• A large page size– keeps page table small.– reduces cache miss times, if accesses have locality– reduces start-up overhead in moving data from disk to memoryf TLB i–means fewer TLB misses• but also– wastes memory (internal fragmentation)– increases the time to start up a programCMSC 411 - 16 (some from Patterson, Sussman, others)4VM and Disk: Page replacement policyPage Table...g1 0useddirty1 0Dirty bit: page written.Udbit tt0 11 10 0Set of all pagesUsed bit: set to1 on any referenceSet of all pagesin MemoryTail pointer:Clear the usedbit in thebit in thepage tableHead pointerPlace pages on free Freelistlist if used bitis still clear.Schedule pages with dirty bit set toHardware Architect’s CMSC 411 - 16 (some from Patterson, Sussman, others)5with dirty bit set tobe written to disk.Free Pagesrole: support setting dirty and used bitsMIPS Address Translation: How does it work?“Physical Addresses”A0-A31A0-A31VirtualPhysical“Virtual Addresses”CPUMemory03A0A31D0-D31 D0-D31TranslationLook-AsideBufferData(TLB)Translation LookAside Buffer (TLB)Translation Look-Aside Buffer (TLB)A small fully-associative cache of mappings from virtual to physical addressesTLB also containsprotection bits for virtual addressFast common case Virt al address is in TLBCMSC 411 - 16 (some from Patterson, Sussman, others)6Fast common case: Virtual address is in TLB, process has permission to read/write it. The TLB caches page table entriesPhysical and virtual pages must be the same size!virtual addressffPhysicalframeaddressPage Table2pageoff01V=0 pages either reside on disk or have not yet been ll t dTLB3physical addresspageoffCMSC 411 - 16 (some from Patterson, Sussman, others)7allocated.OS handles V=0“Page fault”2frame page250MIPS handles TLB misses in software (random replacement). Other machines use hardware.Common OrganizationCPUTLBL1 CacheEven a cachehit requiresTLB translationfirst!Write BufferL2 Cachefirst!Memory busCMSC 411 - 16 (some from Patterson, Sussman, others)8Can TLB and caching be overlapped?IndexByte SelectVirtual Page Number Page OffsetIndexByte SelectValidCache Tags Cache DataTranslationLookAsideVirtualCache BlockgLook-AsideBuffer(TLB)PhysicalCache Block=HitCache TagThis works butHitThis works, but ...Q. What is the downside?CMSC 411 - 16 (some from Patterson, Sussman, others)9A. Inflexibility. Size of cache A. Inflexibility. Size of cache limited by page size.Data outProblems With Overlapped TLB AccessOverlapped access only works as long as the address bits used toindex into the cache do not changeas the result of VA translationgfThis usually limits things to small caches, large page sizes, or highn-way set associative caches if you want a large cacheE l h h h h h Example: suppose everything the same except that the cache isincreased to 8 K bytes instead of 4 K:11 2002012cache indexThis bit is changedby VA translation, buti dd f hvirt page # disp2012is needed for cachelookupSolutions:go to 8K byte page sizes;go to 8K byte page sizes;go to 2 way set associative cache; orSW guarantee VA[13]=PA[13]CMSC 411 - 16 (some from Patterson, Sussman, others)101K44102 way set assoc cacheUse virtual addresses for cache?“Physical Addresses”A0-A31A0-A31VirtualPhysical“Virtual Addresses”CPUMain MemoryA0-A31D0-D31 D0-D31TranslationLook-AsideBuffer(TLB)yCacheVirtualD0-D31O(TLB)Only use TLB on a cache miss !Downside: a subtle, fatal problem. What is it?A. Synonym problem. If two address spaces share a physical frame data may be in cache twice Maintaining,pCMSC 411 - 16 (some from Patterson, Sussman, others)11physical frame, data may be in cache twice. Maintaining consistency is a nightmare. Paging vs. segmentation –Fig. C.21gg ggPage SegmentWords per address One Two (segment/offset)ProgrammerMay be visible to appProgrammer visible?Invisible to app programmerMay be visible to app programmerRli blkTiil(llblk i)Hard (must find contiguous,Replacing a blockTrivial (all blocks same size)Hard (must find contiguous, variable-sized chunk)Memory use Internal fragmentation (within External fragmentation (in inefficiency page) unused memory)Efficient disk traffic Yes (can adjust page size)Not always (small segment problem)CMSC 411 - 16 (some from Patterson, Sussman, others)12Summary #1/3: The Cache Design Space• Several interacting dimensions– cache sizeblock sizeAitiitCache Size–block size– associativity– replacement policywritethrough vs writebackAssociativity–write-through vs write-back– write allocation• The optimal choice is a compromiseBlock Size–depends on access characteristics» workload» use (I-cache, D-cache, TLB)Bad–depends on technology / cost• Simplicity often winsGoodLess MoreFactor A Factor BCMSC 411 - 16 (some from Patterson, Sussman, others)13Summary #2/3: Caches• The Principle of Locality:– Program accesses a relatively small portion of the address space in any short interval of time.» Temporal Locality: Locality in Time» Spatial Locality: Locality in Space• Three Major Categories of Cache Misses:– Compulsory Misses: sad facts of life. Example: cold start misses.– Capacity Misses: increase cache size– Conflict Misses: increase cache size and/or associativity.Nightmare Scenario: ping pong effect!Nightmare Scenario: ping pong effect!• Write Policy: Write Through vs. Write Back• Today CPU time is a function of (ops, cache misses) jtf()fftC il Dt t t dvs. just f(ops): affects Compilers, Data structures, and AlgorithmsCMSC 411 - 16 (some from Patterson, Sussman, others)14Summary #3/3: TLB, Virtual Memory• Page tables map