CS252 S05CMSC 411Computer Systems ArchitectureLecture 10Instruction Level Parallelism 4(Dynamic Scheduling & Tomasulo Algorithm)CMSC 41 1 - 8 (fro m Patter son)Outline• ILP• Compiler techniques to increase ILP• Loop Unrolling• Static Branch Prediction• Dynamic Branch Prediction• Overcoming Data Hazards with Dynamic Scheduling• (Start) Tomasulo Algorithm• Conclusion2CMSC 41 1 - 8 (fro m Patter son)Advantages of Dynamic Scheduling• Dynamic scheduling - hardware rearranges the instruction execution to reduce stalls while maintaining data flow and exception behavior• Handles cases when dependences unknown at compile time – it allows the processor to tolerate unpredictable delays such as cache misses, by executing other code while waiting for the miss to resolve• Allows code that compiled for one pipeline to run efficiently on a different pipeline • Simplifies the compiler • Leads to hardware speculation, a technique with significant performance advantages (discuss later)3CMSC 41 1 - 8 (fro m Patter son)HW Schemes: Instruction Parallelism• Key idea: Allow instructions behind stall to proceedDIVD F0,F2,F4ADDD F10,F0,F8SUBD F12,F8,F14• Enables out-of-order execution and allows out-of-order completion (e.g., SUBD)– In a dynamically scheduled pipeline, all instructions still pass through issue stage in order (in-order issue)• Will distinguish when an instruction begins executionand when it completes execution; between 2 times, the instruction is in execution• Note: Dynamic execution creates WAR and WAW hazards and makes handling exceptions harder4CMSC 41 1 - 8 (fro m Patter son)Dynamic Scheduling Step 1• Simple pipeline had 1 stage to check both structural and data hazards: Instruction Decode (ID), also called Instruction Issue• Split the ID pipe stage of simple 5-stage pipeline into 2 stages: – Issue» Decode instructions, check for structural hazards – Read operands» Wait until no data hazards, then read operands 5CMSC 41 1 - 8 (fro m Patter son)A Dynamic Algorithm: Tomasulo’s• For IBM 360/91 (before caches!)– ⇒ Long memory latency• Goal: High Performance without special compilers• Small number of floating point registers (4 in 360) prevented interesting compiler scheduling of operations– This led Tomasulo to try to figure out how to get more effective registers — renaming in hardware! • Why study a 1966 computer? – The descendants of this have flourished!» Alpha 21264, Pentium 4, AMD Opteron, Power 5, …6CS252 S05CMSC 41 1 - 8 (fro m Patter son)Tomasulo Algorithm• Control & buffers distributed with Function Units (FU)– FU buffers called “reservation stations”; have pending operands• Registers in instructions replaced by values or pointers to reservation stations (RS); called register renaming; – Renaming avoids WAR, WAW hazards– More reservation stations than registers, so can do optimizations compilers can’t7CMSC 41 1 - 8 (fro m Patter son)Tomasulo Algorithm (cont.)• Results to FU from RS, not through registers, over Common Data Bus that broadcasts results to all FUs– Avoids RAW hazards by executing an instruction only when its operands are available• Load and Stores treated as FUs with RSs as well• Integer instructions can go past branches (use branch prediction), also allow FP ops beyond basic block in FP queue8CMSC 41 1 - 10 (fr om Patterson)Tomasulo OrganizationFP addersFP addersAdd1Add2Add3FP multipliersFP multipliersMult1Mult2From MemFP RegistersReservation StationsCommon Data Bus (CDB)To MemFP OpQueueLoad BuffersStore BuffersLoad1Load2Load3Load4Load5Load6From H&P Figure 2.99CMSC 41 1 - 10 (fr om Patterson)10Reservation Station Components• Op: Operation to perform in the unit (e.g., + or –)• Vj, Vk: Value of Source operands– Store buffers have V field, result to be stored• Qj, Qk: Reservation stations producing source registers (value to be written)– Note: Qj,Qk=0 => ready– Store buffers only have Qifor RS producing result• Busy: Indicates reservation station or FU is busyIn addition• Register result status table—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register. CMSC 41 1 - 10 (fr om Patterson)11Three Stages of Tomasulo Algorithm1. Issue—get instruction from FP Op Queue– If reservation station free (no structural hazard), control issues instr & sends operands (renames registers).2. Execute—operate on operands (EX)– When both operands ready then execute;if not ready, watch Common Data Bus for result3. Write result—finish execution (WB)– Write on Common Data Bus to all awaiting units; mark reservation station availableCMSC 41 1 - 10 (fr om Patterson)12Common Data Bus• Normal data bus: data + destination (“go to” bus)• Common data bus: data + source (“come from” bus)– 64 bits of data + 4 bits of Functional Unit sourceaddress– Write if matches expected Functional Unit (produces result)– Does the broadcastCS252 S05CMSC 41 1 - 10 (fr om Patterson)13Tomasulo ExampleInstruction status:Exec WriteInstructionj kIssue Comp ResultBusy AddressLD F6 34+ R2 Load1 NoLD F2 45+ R3 Load2 NoMULTD F0 F2 F4 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2Reservation Stations:S1 S2 RS RSTime NameBusy Op Vj Vk Qj QkAdd1 NoAdd2 NoAdd3 NoMult1 NoMult2 NoRegister result status:ClockF0 F2 F4 F6 F8 F10 F12 ... F300FUClock cycle counterFU countdownInstruction stream3 Load/Buffers3 FP Adder R.S.2 FP Mult R.S.Latencies: LD 1ADD 2MULT 10DIV 40CMSC 41 1 - 10 (fr om Patterson)14Tomasulo Example Cycle 1Instruction status:Exec WriteInstructionj kIssue Comp ResultBusy AddressLD F6 34+ R2 1 Load1 Yes 34+R2LD F2 45+ R3 Load2 NoMULTD F0 F2 F4 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2Reservation Stations:S1 S2 RS RSTime NameBusy Op Vj Vk Qj QkAdd1 NoAdd2 NoAdd3 NoMult1 NoMult2 NoRegister result status:ClockF0 F2 F4 F6 F8 F10 F12 ... F301FULoad1Latencies: LD 1ADD 2MULT 10DIV 40CMSC 41 1 - 10 (fr om Patterson)15Tomasulo Example Cycle 2Instruction status:Exec WriteInstructionj kIssue Comp ResultBusy AddressLD F6 34+ R2 1 Load1 Yes 34+R2LD F2 45+ R3 2 Load2 Yes 45+R3MULTD F0 F2 F4 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2Reservation Stations:S1 S2 RS RSTime NameBusy Op Vj Vk Qj QkAdd1 NoAdd2 NoAdd3 NoMult1 NoMult2 NoRegister result status:ClockF0 F2 F4 F6 F8 F10 F12 ... F302FULoad2 Load1Note: Can have multiple loads