Instruction Set Architecture Instruction set architecture is the interface of a computer that a machine language programmer an operating system designer or a compiler writer must understand to write a correct machine program an operating system a compiler respectively for that machine Chapter 2 Instruction Set Principle and Examples The instruction set architecture is also the interface that a hardware designer must understand to design a correct implementation of the computer Towards Evaluation of ISA and Organization Interface Design A good interface software instruction set Lasts through many implementations Is used in many different ways Provides convenient functionality to higher levels Permits an efficient implementation at lower levels use Interface use hardware use portability compatibility generality imp 1 time imp 2 imp 3 Page 1 1 Evolution of Instruction Sets Machine Instruction Single Accumulator EDSAC 1950 Accumulator Index Registers Manchester Mark I IBM 700 series 1953 Carries out a step of processing Must specify Separation of Programming Model from Implementation Function OPCODE Assume availability of linear address space Input Operand s What to do with results High level Language Based B5000 1963 What to do next Concept of a Family IBM 360 1964 General Purpose Register Machines OPCODE Operand 1 Operand 2 Result Next Complex Instruction Sets Vax Intel 432 1977 80 Four Address Instruction Load Store Architecture CDC 6600 Cray 1 1963 76 RISC Mips Sparc 88000 IBM RS6000 1987 Classifying Instruction Set Architecture Evolution of Instruction Sets Major advances in computer architecture are typically associated with landmark instruction set designs Internal Storage Stack Accumulator Register Ex Stack vs GPR System 360 Design decisions must take into account Operands technology machine organization programming languages compiler technology operating systems And they in turn influence these Number 0 1 2 3 Type Size byte int float Location memory or register effective address Operations Type add sub mul How is it specified Page 2 2 Machine Types Internal Storage Stack Accumulator and Register Machine Type Advantage Stack Simple Model Good code Can not address randomly density Stack Bottleneck Minimizes internal states Highest memory traffic Accumulator Disadvantage Short Instructions Register Most general model for code generation All operands must be named longer instructions C A B Classifying Instruction Set Architecture Emergence of GPR machines Registers Internal Storage Fastest memory Easier for compilers to manipulate Hold variable Stack Accumulator Register Reduce memory traffic Speedup programs Improves code density Operands Number 0 1 2 3 Type Size byte int float Location memory or register effective address Register Load Store most popular Operations Type add sub mul How is it specified How many registers Page 3 3 Characterizing GPR architectures ALU instructions No of Mem Addresses Max NO of Ops per ALU Instruction allowed 0 General Purpose Register Arch Examples Register Register 0 3 2 IBM RT 3 SPARC MIPS PowerPC Alpha Advantages 2 PDP 10 M 68000 IBM 360 Simple Fixed Length Instruction Encoding 3 IBM 360 RS Inst Simple Code Generation Model 2 2 PDP 11 National 32x32 3 3 1 Similar CPI values IBM 360 SS Inst Disadvantages VAX Higher Instruction Count Bit Encoding may be wasteful General Purpose Register Arch General Purpose Register Arch Register Memory 1 2 Memory Memory 3 3 Advantages Advantages No loading first required Most compact Easy to encode with good density does not waste registers for temp info Disadvantages Disadvantages Source operand is destroyed Large variation in instruction size CPI Varies Large variation in work per instruction Encoding a register No in each inst limit Reg No Memory access may create memory bottleneck Page 4 4 Byte Ordering Big Little Endian Memory Addressing byte whose address is x x00 at Ordering of bytes within a word Big endian most significant position IBM mainframes MIPS 680x0 SPARC Alignment 0 Addressing modes 1 2 3 31 0 Big Endian Little endian least significant position Vax Intel 80x86 3 31 2 1 Little Endian 0 0 0 1 ff 08 47 35 2 3 Addressing modes Alignment Addressing mode how architectures specify the address of Access to an object of size s bytes at byte address A is aligned if A mod s 0 an object that they will access Effective address actual memory address specified Mis aligned word reference 32 32 32 To Processor Page 5 5 Addressing Modes Addressing modes Significantly reduce Instruction Count Add to the complexity of Building a Machine May Increase the Average CPI IMPORTANT FACTOR FOR AN ARCHITECT Summary of Use of Memory Addressing Modes Displacement Addressing Mode How large should the displacement field be Directly influence instruction length May have to depend on measurements taken from typical programs Page 6 6 Displacement Values Immediate or Literal Addressing Modes Used in arithmetic operations in comparisons primarily for branches in moves where a constant is needed in a register Constant written in code Small address constants Large Range of Value for Immediates Again directly influence instruction length Again may have to depend on measurements taken from typical programs Displacement of Immediate Values Summary Memory Addressing Expect an architecture to support displacement immediate register deferred These modes represent 75 to 99 of modes used for some typical programs Displacement mode to be 12 to 16 bits Immediate field to be 8 to 16 bits Page 7 7 Classifying Instruction Set Architecture Operations in the Instruction Set Instruction Categories Top 10 Instructions Internal Storage Stack Accumulator Register Operands Number 0 1 2 3 Type Size byte int float Location memory or register effective address Operations Type add sub mul How is it specified Instruction Categories Top 10 Instructions Page 8 8 Control Flow Destination Address 1 Conditional Branches PC Relative 2 Jumps Target often near the current instruction Requires fewer bits Also makes the code Position Independent 3 Procedure Calls 4 Procedure Returns What branch offset should be supported Again influence instruction length and encoding Properties of branch instructions Specifying Branch Condition Large number of the comparisons are simple equalities or inequalities comparisons with zero treat as special cases How to specify branch condition Page 9 9 Destination Address Unknown Procedure Call and Returns Include control transfer and