UMD CMSC 411 - Memory-Hierarchy Design - D1348346

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UMD CMSC 411 - Memory-Hierarchy Design

School name University of Maryland, College Park

Course Cmsc 411- Computer Systems Architecture

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1Page1Memory-HierarchyDesignWhyismemoryimportant?1101001000198019811982198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPU• MemorywallduetoemphasisonspeedforprocessordensityforDRAMCPU-DRAMSpeedGapTheGoalProvidememorysystemwithcostofcheapest levelofmemoryandwithspeedasfastasfastest levelofmemoryInstructioncacheUnifiedcacheDatacacheDRAMmemorySecondarystorageCPU(registers)UpperlevelLowerlevelMemoryHierarchyL1cacheL2cache• Thecorrectnesscriteria– Theexecutionresultsofaprogramshouldbeas if itwereexecutedonasystemwithoutanycachememory2Page2GeneralCachingPrinciples• Locality– TemporalLocality:referencedagainsoon– SpatialLocality:nearbyitemsreferencedsoon• Locality+smallerHWisfaster=memoryhierarchy– Levels:eachsmaller,faster,moreexpensive/bytethanlevelbelow– Inclusive:datafoundintopalsofoundinthebottomSomeDefinitions• Upperisclosertoprocessor• Block:minimumunitofinformationthatcanbepresentincache• Hittime:timetoaccesscache,includinghitdetermination• Hitrate:fractionfoundinthecache- Missrate=1- HitRate• Misspenalty:timetofetchablockfromlowerlevel,includingtimetoreplaceinCPU- accesstime:timetoaccesslowerlevel- transfertime:timetotransferblockDifferencesinMemoryLevelsFourQuestionsforMemoryHierarchyDesigners• Q1:Wherecanablockbeplacedintheupperlevel?(Blockplacement)• Q2:Howisablockfoundifitisintheupperlevel?(Blockidentification)• Q3:Whichblockshouldbereplacedonamiss?(Blockreplacement)• Q4:Whathappensonawrite?(Writestrategy)3Page3Q1:Wherecanablockbeplacedintheupperlevel?• DirectMapped:Eachblockhasonlyoneplacethatitcanappearinthecache.• Fullyassociative:Eachblockcanbeplacedanywhereinthecache.• Setassociative:Eachblockcanbeplacedinarestrictedsetofplacesinthecache.– Iftherearenblocksinaset,thecacheplacementiscalledn-waysetassociativeAssociativity ExamplesFullyassociative:Block12cangoanywhereDirectmapped:Blockno.=(Blockaddress)mod(#ofblocksincache)Block12cangoonlyintoblock4(12mod8)Setassociative:Setno.=(Blockaddress)mod(#ofsetsincache)Block12cangoonlyintoset0(12mod4)butanyblockinthatsetQ2:HowIsaBlockFoundIfItIsintheUpperLevel?• Theaddresscanbedividedintotwomainparts– Blockoffset:selectsthedatafromtheblockoffsetsize=log2(blocksize)– Blockaddress:tag+index» index:selectssetincacheindexsize=log2(#ofsets)=log2(#ofblocks/set associativity)» tag:comparedtotagincachetodeterminehittagsize=addresssize- indexsize- offsetsizeMappingFunction4Page4MappingFunctionConsider• 64KBcache• 4Bytedatatransfer(block)sizebetweenmainmemoryandcache• CacheOrganizedin16Kblockframes(slots)of4Byteseach• Mainmemoryhas16MBytes(Orwecantreatthememoryashaving4Mblocksof4Byteseach)24bitmemoryaddressMappingStructureMainMemoryCache0 1RowNumberColumnNumberRowNumberColumnNumberMappingStructureMapping Rows Columns Rows ColumnsDirect 256 16K 1 16KAssociative 4M 1 16K 1SetAssociative 512 8K 2 8KMainMemory CacheDirectMapping14BitsindexNo28BitsTag5Page5AssociativeMapping222bittagSetAssociativeMapping2139Tag IndexBlockOffsetAddressMatchtoCacheBlockOffsetIndexTag.....8.3vValidbit---->Tagsearch---->Datablock--->2-waysetassociativecacheQ3:WhichBlockShouldbeReplacedonaMiss?• DirectMapped:– NoChoice(onlyonecandidate)• SetAssociativeorFullyAssociative:– Random- easiertoimplementbutlessefficient– LeastRecentlyused- hardertoimplementbutmoreefficient• Missratesforcacheswithdifferentsize, associativity andreplacementalgorithm.6Page6Q4:WhatHappensonaWrite?• Writethrough:Theinformationiswrittentoboththeblockinthecacheandtotheblockinthelower-levelmemorycombinedwithwritebufferssoitwon’twaitforlowerlevelmemoryaccess• Writeback:Theinformationiswrittenonlytotheblockinthecache.Themodifiedcacheblockiswrittentomainmemoryonlywhenitisreplaced.– isblockcleanordirty?(addadirtybittoeachblock)• ProsandConsofeach(obviousones):– Writethrough» readmissescannotresultinwritestomemory,» easiertoimplement» mainmemoryis“always” up-to-date(lesscoherenceproblem)– Writeback» Lessmemorytraffic» PerformwritesatthespeedofthecacheQ4:WhatHappensonaWrite?• Sincedatadoesnothavetobebroughtintothecacheonawritemiss,therearetwooptions:– Writeallocate» Theblockisbroughtintothecacheonawritemiss» Usedmostlywithwrite-backcaches» Hopesubsequentaccessestotheblockhitincache– No-writeallocate» Theblockismodifiedinmemory,butnotbroughtintothecache» Usedwithwrite-throughcaches»

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