1Page1MemoryHierarchyandCacheDesign(4)Virtualvs RealAddressSpacesVirtualAddressSpaceRealAddressSpaceMappingVirtualMemory- thelogicalconceptVirtualMemoryvs Cache2Page2VirtualMemoryvs Cache• Replacement– Cache- controlledbyhardware– Virtualmemory- controlledbyoperatingsystem» HUGEmisspenalty• Size– Virtualmemorysizeisdeterminedbyprocessoraddresssize– Cachesizeisindependentofprocessoraddresssize• Combinedusageofsecondarymemory– Backingstoreofmainmemory– FilesystemTypesofVirtualMemory• Paged– Fixedsizeblocks(pages)– Sizeusually4K-64Kbytes• Segmented– Variablesizeblocks– SizesvaryMappingRealAddressSpaceVirtualAddressSpaceBlockBaseValueR=V+(BaseRegister)MappingrequiresoneBaseValueforeachblockBlocksmaybeofsamesizeorvaryingsizeSegmentationandPaging• Segmentation– OrganizeVirtualAddressSpaceinvariablesizeblocks– Needinformationaboutthelengthofblocksalso– Addressesfromonesegmenttothenextmaynotbeconsideredcontiguous– Virtualaddress» {SegmentID,OffsetinSegment}• Paging– OrganizeVirtualAddressSpaceinfixedsizeblocks– VirtualAddress» {SingleAddress}3Page3Segmentationvs PagingSegmentationvs PagingExternalFragmentation segment1segment2segment3segment4 doesn'tfitsegment5InternalFragmentationprocess1process2page1page2page3page4page5page64Page4TranslatingVirtualAddressesBlock OffsetOffsetTranslationTableSegmentationseg no. offsetwithinsegmentUser'saddressP lengthstartaddr.+physicaladdressPagingAddressTranslationFourQuestionsforVirtualMemory• BlockPlacement:FullyAssociative• BlockIdentification:FullyAssociative• BlockReplacement:LRUoritsvariants• WriteStrategy: Writeback&Writeallocate5Page5BlockPlacement• FullyAssociative- theobviouschoice– Hugemisspenalty- lowmissrateisextremelyimportant– VMmanagedbysoftwareinOS- muchmoreflexiblethancachemanagedbyhardwareBlockIdentificationPagingLogicaltoPhysicalAddressesVAXMemoryManagement• 32Bitaddresses• 4GBVirtualAddressSpace• 512Bytesperpage2**23pages• RealAddressSpaceislimitedto1GB2**21PageFrames6Page6AddressTranslationBlockReplacement• PureLRUisdifficult,ifnotimpossible,toimplement• TheClockAlgorithm– Maintainacircularlistofpagesinphysicalmemory» Useause bittotrackhowrecentlyapageisreferenced» Use bitsetwheneverapageisreferenced– Onapagefault,lookforapagewithuse bit=0(intheclockorder)» Replacesapagethathasn’tbeenreferencedforonecompleterevolutionoftheclockWriteStrategy• Writeback- theobviouschoiceFastAddressTranslation• Pagetablesarelargeandoftenpaged• Needfastmechanismforaddresstranslation• USE– TRANSLATIONLOOK-ASIDEBUFFERS(TLB)– Associativememory7Page7TLB:PageTableCacheTLBMoreDetailsonTLB(AlphaAXP21064TLB)PageSize• Sizeofpagetableisinverselyproportionaltothepagesize• Transferringlargerpagestoandfromthesecondarystorageismoreefficientthansmallerpages• AsTLBsizesarerestricted,largerpagesizesimplymoreaddressspacecanbetranslated• Largerpagesizesleadtohigherinternalfragmentation• LargerpagesleadtohigherstartuptimeforaprocessSegmentationandPagingseg no. offsetwithinthesegmentsegmenttablepagetablerealaddress8Page8SegmentationandPagingSegmentation Paging1.Blocksize Variable Fixed2.Placement Firstfit,etal. Fullyassociative3.Howfound Size+location Pagetableregisters4.Replacement byprogrammer LRU5.Writeaction Writeback WritebackFragmentation External InternalProgramming Visible TransparentProtection RO,RW,EX DifficultProtection• Haveboundsregisterandcheckitforeachaccess– Haveatleasttwomodes- KernelandUser– HaveCPUstatesthatcanbeusedbyauserbutnotmodified- BaseandBoundRegisters...– Controlledchangeofmode- SystemCallExample- AXP21064• 64-bitaddresses– kseg - (bits63and62=10)»
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