Computer Systems Architecture CMSC 411 Unit 6 Storage Systems Alan Sussman November 23 2004 Storage systems We already know about four levels of storage registers cache memory disk but we ve been a little vague on how these devices are interconnected In this unit we study input output units such as disks and tapes buses to connect storage devices I O performance issues design of file systems won t talk much about this CMSC 411 Alan Sussman CMSC 411 A Sussman from D O Leary 2 1 Disk and Tape Technologies Hard Disks What it is a collection of 1 20 platters like 2 sided CD s between 1 and 8 inches in diameter 2 5 3 5 inch most common today rotating on a central spindle with 500 2500 tracks on each surface divided into maybe 64 sectors older disks all tracks have the same number of sectors current disks outer tracks have more sectors larger diameter best retrieval times smaller diameter cheaper and uses less power CMSC 411 Alan Sussman CMSC 411 A Sussman from D O Leary 4 2 Disks cont Fig 7 1 Used for file storage slowest level of virtual memory during program execution CMSC 411 Alan Sussman 5 Disks cont How information is retrieved Wait for previous requests to be filled Time queuing delay A movable arm is positioned at the correct cylinder Time seek time The system waits for the correct sector to appear under the arm Time rotational latency Then a magnetic head senses the sector number the information recorded in the sector an error correction code CMSC 411 Alan Sussman CMSC 411 A Sussman from D O Leary 6 3 Disks cont and the information is transferred to a buffer Time transfer time The retrieval is handled by a disk controller which may impose some extra overhead Time controller time Because all of this is so expensive might also read the next sector or two hoping that the next information needed is located there prefetch or read ahead CMSC 411 Alan Sussman 7 Example average seek 5 ms time transfer rate 10MB sec rotation speed sector size 8000 RPM controller overhead 5 ms 1024 bytes Average disk access time in millisec average seek time average rotational delay transfer time controller overhead CMSC 411 Alan Sussman CMSC 411 A Sussman from D O Leary 8 4 Example cont average seek time 5 ms average rotational delay 0 5 0 5 3 75ms 8 000 RPM 8 000 60 RPS transfer time 1KB 103 bytes 7 10 4 sec 1ms 10MB sec 10 bytes sec controller overhead 5 ms Total 5 3 75 1 5 9 35 ms CMSC 411 Alan Sussman 9 Computer Systems Architecture CMSC 411 Unit 6 Storage Systems Alan Sussman November 30 2004 CMSC 411 A Sussman from D O Leary 5 Administrivia HW 5 due today Project due Friday questions Quiz 3 scheduled for Dec 7 practice quiz posted by tomorrow Online course evaluation available at https www courses umd edu online evalua tion CMSC 411 Alan Sussman 11 Last time Speculation can provide precise exceptions ROB can issue multiple instructions per clock and commit multiple per clock don t speculate on expensive events e g 2nd level cache misses can speculate through multiple branches P6 microarchitecture generate RISC like micro operations for each IA 32 instruction out of order speculative pipeline with ROB CMSC 411 Alan Sussman CMSC 411 A Sussman from D O Leary 12 6 Last time cont Storage systems how a disk works platters tracks cylinders sectors retrieval costs queuing delay wait for previous requests seek time find the right track rotational latency find the right sector transfer time read the data into a buffer and sector number ECC controller time overhead in disk controller CMSC 411 Alan Sussman 13 Technology gap between memory and disk Fig 7 5 CMSC 411 Alan Sussman CMSC 411 A Sussman from D O Leary 14 7 Competitors to disks solid state disks built from DRAMs but needs constant power optical disks CDs and DVDs magnetic tapes slower but large capacity good for backups automated tape libraries juke box technology flash memory small fast low power CMSC 411 Alan Sussman 15 Buses CMSC 411 A Sussman from D O Leary 8 Buses We ve seen buses before especially in the discussion of Tomasulo s algorithm Main characteristic Buses are shared by several data paths and therefore can be bottlenecks CPU memory buses physically short high speed design optimized for performance I O buses long handle an unknown number of devices with unpredictable characteristics CMSC 411 Alan Sussman 17 Typical bus transaction When a READ is issued Bus begins in a wait state Address sent on bus to memory with control information to signal a read When data is available the wait signal is turned off and the data is transmitted When a WRITE is issued Bus begins in a wait state Address sent on bus to memory with control information to signal a write Then the data is transmitted usually with no pause CMSC 411 Alan Sussman CMSC 411 A Sussman from D O Leary 18 9 Bus options Fig 7 8 Option High performance Low cost Bus width separate address and data lines multiplex address and data lines Data width wider is faster e g 64 bits narrower is cheaper e g 8 bits Transfer size multiple words have less overhead single word transfer is simpler Bus masters multiple need arbitration single no arbitration Split transactions yes separate request and reply gets higher bandwidth no continuous connection cheaper and lower latency Clocking asynchronous synchronous CMSC 411 Alan Sussman 19 Who issues READs and WRITEs The bus master does If the bus is between CPU and memory then the CPU is the bus master If it is an I O bus then there might be several devices so several bus masters and they compete for time slices on the bus In this case buses are often packet switched each device divides its message into fixed length packets and takes turns with other devices that are transmitting CMSC 411 Alan Sussman CMSC 411 A Sussman from D O Leary 20 10 Synchronous vs asynchronous buses Buses that are clocked synchronous send data and addresses at fixed times so sender and receiver always know what to expect Makes them fast and cheap But restricts them to be short because of time lag problems Buses that are not clocked asynchronous use handshaking protocols to establish contact Sender puts message on bus to get the attention of receiver Receiver responds Sender transmits data Receiver sends acknowledgement of receipt CMSC 411 Alan Sussman 21 Asynchronous buses Because of handshaking protocol They can be slow and expensive But it allows them to be physically long and to serve a wide variety of devices The handshaking protocols are standardized so that device