Administrivia Wanli will give lecture on Thursday Exam 1 answers posted CMSC 411 Computer Systems Architecture Lecture 11 Instruction Level Parallelism cont Mean 67 Median 66 Standard Dev 12 5 Homework 3 posted from H P Chapter 2 due d March M h 24 Read Chapter 3 of H P but not too deeply there s way too much detail in the experiments comparisons Alan Sussman als cs umd edu l d d 2 CMSC 411 11 from Patterson Reorder Buffer operation Holds instructions in FIFO order exactly as issued When instructions complete results placed into ROB Supplies operands to other instruction between execution complete commit more registers like RS Tag results with ROB buffer number instead of reservation station IInstructions i commit i values l at h head d off ROB placed l d iin registers Reorder As a result easy to undo Buffer speculated instructions FP Op on mispredicted branches Queue FP Regs or on exceptions ADDING SPECULATION TO TOMASULO S TOMASULO S ALGORITHM Commit path Res Stations FP Adder CMSC 411 11 from Patterson 3 CMSC 411 11 from Patterson Res Stations FP Adder 4 Recall 4 Steps p of Speculative p Tomasulo Algorithm g Tomasulo With Reorder buffer Done FP Op Queue ROB7 ROB6 1 Issue get instruction from FP Op Queue ROB5 Reorder Buffer If reservation station and reorder buffer slot free issue instr send operands reorder buffer no for destination this stage sometimes called dispatch ROB4 ROB3 2 Execution operate on operands EX ROB2 F0 When both operands ready then execute if not ready watch CDB for result when both in reservation station execute checks RAW sometimes called issue Write on Common Data Bus to all awaiting FUs reorder buffer mark reservation station available Dest When instr at head of reorder buffer result present update register with result or store to memory and remove instr from reorder buffer Mispredicted branch flushes reorder buffer sometimes called graduation FP adders dd ROB7 ROB6 Dest 1 10 R2 FP multipliers lti li 6 CMSC 411 11 from Patterson Newest Done FP Op Queue ROB7 ROB6 ROB5 Reorder Buffer Registers Dest 2 ADDD R F4 ROB1 FP adders dd Reorder Buffer ROB3 N N ROB2 ROB1 Oldest Dest 2 ADDD R F4 ROB1 from y Memory Reservation Stations Dest 1 10 R2 FP multipliers lti li CMSC 411 11 from Patterson ROB4 F2 F10 F0 DIVD F2 F10 F6 ADDD F10 F4 F0 LD F0 F0 10 R2 10 R2 Registers To Memory Dest Newest ROB5 ROB4 ADDD F10 F4 F0 LD F0 F0 10 R2 10 R2 Oldest Tomasulo With Reorder buffer Done FP Op Queue ROB1 from y Memory Reservation Stations 5 Tomasulo With Reorder buffer N To Memory Dest 4 Commit 4 Commit update update register with reorder result CMSC 411 11 from Patterson LD F0 F0 10 R2 10 R2 Registers 3 Write result finish 3 result finish execution WB F10 F0 Newest FP adders dd 7 N N N ROB3 ROB2 ROB1 Oldest To Memory Dest 3 DIVD ROB2 R F6 ROB2 R F6 Reservation Stations from y Memory Dest 1 10 R2 FP multipliers lti li CMSC 411 11 from Patterson 8 Tomasulo With Reorder buffer Tomasulo With Reorder buffer Done FP Op Queue ROB7 Reorder Buffer F0 F4 F2 F10 F0 ADDD F0 F4 F6 LD F4 0 R3 BNE F2 DIVD F2 F10 F6 ADDD F10 F4 F0 LD F0 F0 10 R2 10 R2 Registers Dest 2 ADDD R F4 ROB1 6 ADDD ROB5 ROB5 R F6 FP adders dd N N N N N N ROB6 Newest ROB5 Reorder Buffer ROB4 ROB3 ROB2 ROB1 Oldest Dest 3 DIVD ROB2 R F6 ROB2 R F6 FP multipliers lti li Dest 2 ADDD R F4 ROB1 6 ADDD ROB5 ROB5 R F6 from y Memory Dest 1 10 R2 5 0 R3 FP adders dd Tomasulo With Reorder buffer Reorder Buffer M 10 F0 F4 M 10 F2 F10 F0 ST 0 R3 F4 ADDD F0 F4 F6 LD F4 0 R3 BNE F2 DIVD F2 F10 F6 ADDD F10 F4 F0 LD F0 F0 10 R2 10 R2 Registers Dest 2 ADDD R F4 ROB1 6 ADDD M 10 M 10 R F6 R F6 FP adders dd Reservation Stations Dest 3 DIVD ROB2 R F6 ROB2 R F6 Newest Oldest FP multipliers lti li from y Memory Dest 1 10 R2 5 0 R3 10 CMSC 411 11 from Patterson Done Y ROB7 N ROB6 Y ROB5 N ROB4 N ROB3 N ROB2 N ROB1 Newest FP Op Queue Reorder Buffer Oldest M 10 F0 val2 F4 M 10 F2 F10 F0 Done ST 0 R3 F4 Y ROB7 ADDD F0 F4 F6 Ex ROB6 LD F4 0 R3 Y ROB5 BNE F2 N ROB4 DIVD F2 F10 F6 N ROB3 ADDD F10 F4 F0 N ROB2 LD F0 F0 10 R2 10 R2 N ROB1 Registers Dest 2 ADDD R F4 ROB1 from y Memory Dest 1 10 R2 FP multipliers lti li CMSC 411 11 from Patterson Done N ROB7 N ROB6 N ROB5 N ROB4 N ROB3 N ROB2 N ROB1 Tomasulo With Reorder buffer To Memory Dest 3 DIVD ROB2 R F6 ROB2 R F6 ST 0 R3 F4 ADDD F0 F4 F6 LD F4 0 R3 BNE F2 DIVD F2 F10 F6 ADDD F10 F4 F0 LD F0 F0 10 R2 10 R2 To Memory Reservation Stations 9 CMSC 411 11 from Patterson ROB5 F0 F4 F2 F10 F0 Registers To Memory Reservation Stations FP Op Queue FP Op Queue FP adders dd 11 Newest Oldest To Memory Dest 3 DIVD ROB2 R F6 ROB2 R F6 Reservation Stations from y Memory Dest 1 10 R2 FP multipliers lti li CMSC 411 11 from Patterson 12 Tomasulo With Reorder buffer Tomasulo With Reorder buffer Done FP Op Queue ROB7 ROB6 Reorder Buffer F4 M 10 F2 F10 F0 LD F4 0 R3 BNE F2 DIVD F2 F10 F6 ADDD F10 F4 F0 LD F0 F0 10 R2 10 R2 Registers Dest 2 ADDD R F4 ROB1 FP adders dd Y N N N N Newest Reservation Stations ROB7 ROB6 ROB5 Reorder Buffer ROB4 ROB3 ROB2 Oldest ROB1 What about memory hazards Dest 2 ADDD R F4 ROB1 from y Memory Dest 1 10 R2 FP multipliers lti li CMSC 411 11 from Patterson F4 M 10 F2 F10 F0 LD F4 0 R3 BNE F2 DIVD F2 F10 F6 ADDD F10 F4 F0 LD F0 F0 10 R2 10 R2 Registers To Memory Dest 3 DIVD ROB2 R F6 ROB2 R F6 Done FP Op Queue FP adders dd 13 Dest 3 DIVD ROB2 R F6 ROB2 R F6 Reservation Stations ROB3 ROB2 ROB1 Oldest Dest 1 10 R2 FP multipliers lti li CMSC 411 11 from Patterson WAW and WAR hazards through memory are eliminated with speculation because actual updating of memory occurs in order d when h a store t iis att h head d off th the ROB ROB and dh hence no earlier loads or stores can still be pending IBM 360 91 invented imprecise interrupts RAW hazards through memory are maintained by two restrictions t i ti Technique …
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