Shift RegistersRipple CounterSynchronous CounterGeneral Binary CountersA Modulus N+1 CounterA Clock dividerA Balanced Clock dividerVHDL for a simple counterSynch and Asynch ControlsSeattle Pacific University EE 1210 - Logic System Design Counters-1Shift RegistersD QclkD QD QShiftInQ3Q2D QQ1Q0A shift register shifts all bits one to the right (or left) each clock period? ? ? ?00 ? ? ?11 0 ? ?00 1 0 ?0 0 0 1 01 1 0 0 11010010010011?010??01???0????Q0Q1Q2Q3Shift registers are useful for converting serial (one bit at a time) data to parallel (multiple bits at a time)Seattle Pacific University EE 1210 - Logic System Design Counters-2Ripple Counter‘1’C0‘1’‘1’C1C2ClockC1C2clockC00 1 0 1 0 1A 3-bit asynchronous counter0 0 1 1 0 00 0 0 0 1 1Note the cumulative delays in changing of bitsTQQTQQTQQC2C1C0 0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1When one bit changes from one to zero, next bit should toggleSeattle Pacific University EE 1210 - Logic System Design Counters-3Synchronous Counter‘1’TQQC0TQQC1TQQC2ClockC1C0A 3-bit synchronous counterC2000 001 010 011 100 101Note that all bits change at the same timeclockC0C0C1C2C1C0 0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1When previous bits are all ones, next bit should toggleSeattle Pacific University EE 1210 - Logic System Design Counters-4General Binary CountersQ[7..0]CLKD[7..0]ENLDCLR8-bitCounterQ – Count Value (Output)Edge-triggered clockD – Parallel load valueLD – Parallel loadEN – Count enableCLR – Set to zeroLoad and CLR may be synchronous or asynchronousSeattle Pacific University EE 1210 - Logic System Design Counters-5A Modulus N+1 CounterQ[7..0]CLKENSCLR8-bitCounterWhenever count >= N, clear counterCompareA[7..0]B[7..0]A>=BN‘1’CLK0,1,2,3,4,…,N,0,1,2,…Requires synchronous clearSeattle Pacific University EE 1210 - Logic System Design Counters-6A Clock dividerQ[19..0]CLKENSCLR20-bitCounterCount clock ticks When reach 1,000,000, clear counterCompareA[19..0]B[19..0]A>=B1,000,000‘1’1 MHz CLKConvert a 1MHz clock into a 1Hz clock by dividing by 1,000,0001 Hz CLKCounter must have enough bits to reach compare value (1,000,000)WARNING: Clock is unbalanced: On for 1us, off for 999,999usSeattle Pacific University EE 1210 - Logic System Design Counters-7A Balanced Clock dividerQ[19..0]CLKENSCLR20-bitCounterCompareA[19..0]B[19..0]A>=B500,000‘1’1 MHz CLKConvert a 1MHz clock into a 50% duty cycle 1Hz clock by dividing by 500,000 and toggling output2 Hz Unbalanced CLKTQQ1 MHz CLK1 Hz 50% d.c. clockToggle clock every 0.5s (500,000 clock cycles)Seattle Pacific University EE 1210 - Logic System Design Counters-8VHDL for a simple counterLIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;ENTITY count8 ISPORT( CLK : IN STD_LOGIC;EN: IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END count8;ARCHITECTURE behavior OF count8 ISSIGNAL Count: STD_LOGIC_VECTOR(7 DOWNTO 0)); BEGINPROCESS(CLK)BEGIN IF RISING_EDGE(CLK) THEN IF (EN=‘1’) THEN Count <= Count+1; ELSE Count <= Count; END IF; END IF;END PROCESS;Q <= Count;END behavior;Inputs: CLK and en Output: Q (eight bits)Requires an internal signal for the count (can’t use the output Q for this)If enabled, increment count; if not, don’t change itNote: Need unsigned library to do mathAssign the output (Q) the value of countSeattle Pacific University EE 1210 - Logic System Design Counters-9Synch and Asynch ControlsARCHITECTURE behavior OF count8LC ISSIGNAL Count: STD_LOGIC_VECTOR(7 DOWNTO 0)); BEGINPROCESS(CLK,CLR)BEGINIF (CLR=‘1’) THENCount <= “00000000”;ELSIF RISING_EDGE(CLK) THENIF (LOAD = ‘1’) THENCount <= D;ELSIF (EN=‘1’) THENCount <= Count + 1;ELSECount <= Count;END IF;END IF;END PROCESS;Q <= Count;END behavior;Add a synchronous load and an asynchronous clearSince CLR may come at any time, add to PROCESSLOAD only happens on rising edge  inside check for rising edgeNote: Entity not shown due to space limitationsCLR is outside of check for rising