Shift Registers A shift register shifts all bits one to the right or left each clock period ShiftIn 0 D 1 Q3 Q 1 D 0 Q2 Q 0 D 1 Q1 Q 0 D 1 Q0 Q 1 0 clk Q3 Q2 Q1 Q0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 0 Seattle Pacific University Shift registers are useful for converting serial one bit at a time data to parallel multiple bits at a time EE 1210 Logic System Design Counters 1 Ripple Counter C0 T 1 Q Q C1 T 1 Q C2 1 T Q Q Q clock A 3 bit asynchronous counter C2 C1 C0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 When one bit changes from one to zero next bit should toggle Clock C0 C1 C2 0 00 0 01 0 10 0 11 1 00 1 01 Note the cumulative delays in changing of bits Seattle Pacific University EE 1210 Logic System Design Counters 2 Synchronous Counter C0 1 T Q C1 C0 Q T Q Q C1 C0 C2 T C2 C1 C0 0 0 0 0 1 1 1 1 Q Q clock A 3 bit synchronous counter 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 When previous bits are all ones next bit should toggle Clock C0 C1 C2 000 001 010 011 100 101 Note that all bits change at the same time Seattle Pacific University EE 1210 Logic System Design Counters 3 General Binary Counters Q Count Value Output D Parallel load value D 7 0 LD Parallel load LD CLR Set to zero CLR EN Count enable EN Q 7 0 8 bit Counter CLK Edge triggered clock Load and CLR may be synchronous or asynchronous Seattle Pacific University EE 1210 Logic System Design Counters 4 A Modulus N 1 Counter Q 7 0 0 1 2 3 4 N 0 1 2 A 7 0 A B N SCLR B 7 0 Compare 1 EN 8 bit Counter Whenever count N clear counter CLK CLK Requires synchronous clear Seattle Pacific University EE 1210 Logic System Design Counters 5 A Clock divider Convert a 1MHz clock into a 1Hz clock by dividing by 1 000 000 1 000 000 Count clock ticks When reach 1 000 000 clear counter Q 19 0 A 19 0 A B B 19 0 Compare SCLR 1 WARNING Clock is unbalanced On for 1us off for 999 999us 1 Hz CLK EN 20 bit Counter CLK 1 MHz CLK Counter must have enough bits to reach compare value 1 000 000 Seattle Pacific University EE 1210 Logic System Design Counters 6 A Balanced Clock divider Convert a 1MHz clock into a 50 duty cycle 1Hz clock by dividing by 500 000 and toggling output 500 000 Toggle clock every 0 5s 500 000 clock cycles Q 19 0 A 19 0 A B B 19 0 Compare SCLR 2 Hz 1 Unbalanced CLK T EN Q 20 bit Counter CLK 1 MHz CLK 1 Hz 50 d c clock Q 1 MHz CLK Seattle Pacific University EE 1210 Logic System Design Counters 7 VHDL for a simple counter LIBRARY ieee USE ieee std logic 1164 all USE ieee std logic unsigned all Inputs CLK and en Output Q eight bits ENTITY count8 IS Note Need unsigned library to do PORT CLK IN STD LOGIC math EN IN STD LOGIC Q OUT STD LOGIC VECTOR 7 DOWNTO 0 END count8 ARCHITECTURE behavior OF count8 IS SIGNAL Count STD LOGIC VECTOR 7 DOWNTO 0 BEGIN PROCESS CLK Requires an internal signal for the BEGIN count can t use the output Q for this IF RISING EDGE CLK THEN IF EN 1 THEN Count Count 1 ELSE If enabled increment count if not Count Count don t change it END IF END IF END PROCESS Assign the output Q the value of count Q Count END behavior Seattle Pacific University EE 1210 Logic System Design Counters 8 Synch and Asynch Controls Add a synchronous load and an asynchronous clear Note Entity not shown due to space limitations ARCHITECTURE behavior OF count8LC IS SIGNAL Count STD LOGIC VECTOR 7 DOWNTO 0 BEGIN PROCESS CLK CLR Since CLR may come at any time add to PROCESS BEGIN IF CLR 1 THEN Count 00000000 CLR is outside of check for rising edge ELSIF RISING EDGE CLK THEN IF LOAD 1 THEN Count D ELSIF EN 1 THEN LOAD only happens on rising edge Count Count 1 inside check for rising edge ELSE Count Count END IF END IF END PROCESS Q Count END behavior Seattle Pacific University EE 1210 Logic System Design Counters 9