MultiplexersSlide 2VHDL MuxesCascading MuxesUsing Muxes as logic blocksOptimized LUTsUsing a multiplexor as a switchUsing a BusSmoke Happens…Tri-State InverterUsing tri-state gatesDemultiplexersLarger Demultiplexers/DecodersDecoders In VHDLEncodersPriority EncodersVHDL Priority EncoderSeattle Pacific University EE 1210 - Logic System Design Mux-Decoder-1MultiplexersTwo alternative formsfor a 2:1 Mux Truth TableFunctional formLogical formI 1 0 0 0 0 1 1 1 1 I 0 0 0 1 1 0 0 1 1 S 0 1 0 1 0 1 0 1 Z 0 0 1 0 0 1 1 1 S 0 1 Z I 0 I 1 A digital n-to-1 switch is called a multiplexer (or a selector)Z = S' I0 + S I1I 0 I 1 Z SS=0S=12:1MultiplexorSeattle Pacific University EE 1210 - Logic System Design Mux-Decoder-2MultiplexersZ SI SI 0 1Z S S I S S I S S I S S I   1 0 0 1 0 1 1 0 2 1 0 3Z S S S I S S S I S S S I S S S IS S S I S S S I S S S I S S S I       2 1 0 0 2 1 0 1 2 1 0 2 2 1 0 32 1 0 4 2 1 0 5 2 1 0 6 2 1 0 7I 0 S2 I 1 I 2 I 3 S1 Z 8:1 mux S0I 4 I 5 I 6 I 7 I 0 S1 I 1 I 2 I 3 S0 Z 4:1 mux 2:1 mux I 0 I 1 SZSeattle Pacific University EE 1210 - Logic System Design Mux-Decoder-3VHDL MuxesLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY mux4to1 ISPORT( data : IN STD_LOGIC_VECTOR(3 downto 0); sel : IN STD_LOGIC_VECTOR(1 downto 0); z : OUT STD_LOGIC);END mux4to1;Remember the IEEE library!ARCHITECTURE behavior OF mux4to1 ISBEGINPROCESS(data,sel)BEGINCASE sel ISWHEN "00" => z <= data(0);WHEN "01" => z <= data(1);WHEN "10" => z <= data(2);WHEN "11" => z <= data(3);WHEN others => z <= 0; END CASE;END PROCESS;END behavior;Inputs: data[3..0],sel[1..0]Output: ZSet up as a CASE statementWHEN OTHERS – Use this even if there aren’t any othersIf Data or Sel change, output (Z) can changeSeattle Pacific University EE 1210 - Logic System Design Mux-Decoder-4Cascading MuxesLarge multiplexers can be implemented by cascaded smaller muxesControl signals S1 and S0 simultaneouslychoose one of I0-I3 and I4-I7Control signal S2 chooses which of theupper or lower MUX's output to gate to ZAlternative 8:1 Mux Implementation01S01S01S01S01S023S1S2S1S0ZI0 I1 I2 I3 I4 I5 I6 I7 S0S0S04:1 mux 4:1 mux 8:1 mux 2:1 mux 0 1 2 3 0 1 2 3 S S 1 S 0 S 1 S 0 S2S0S1 I0 0 1 I1 I2 I3 I4 I5 I6 I7 ZSeattle Pacific University EE 1210 - Logic System Design Mux-Decoder-5Using Muxes as logic blocks2n-1:1 multiplexer can implement any function of n variablesn-1 control variables; remaining variable is a data input to the muxF(C,B,A) = m0 + m2 + m6 + m7Lookup TableC 0 0 0 0 1 1 1 1B 0 0 1 1 0 0 1 1A 0 1 0 1 0 1 0 1F 1 0 1 0 0 0 1 18:1 MUX1 0 1 0 0 0 1 10 1 2 3 4 5 6 7 S2 S1 S0C B AF0 101Seattle Pacific University EE 1210 - Logic System Design Mux-Decoder-6Optimized LUTsF(C,B,A) = m3 + m4+ m6 + m7C BS1 S04:1 MUX0 1 2 3A01AFWe can fit a function of n variables into a 2n-1:1 mux by using this trick (note: may require one inverter)C0 0 0 0 1 1 1 1B 0 0 1 1 0 0 1 1A 0 1 0 1 0 1 0 1F 0 0 0 1 1 0 1 1A01ACB=00; F=0CB=01; F=ACB=10; F=A’CB=11; F=1Seattle Pacific University EE 1210 - Logic System Design Mux-Decoder-7Using a multiplexor as a switchConsider a computer system with CPU, memory, I/O devices, etc.Each one needs to be able to communicate with the others… MemoryCPUDiskKeyboard4:1 x 32bit Mux3232323232ControlPros:• Conceptually simpleCons:• Lots of wires…• Each device needs separate output and input ports• 32-bit mux is a large device Example: Read a value from memory into CPU00Seattle Pacific University EE 1210 - Logic System Design Mux-Decoder-8Using a BusBus – Bidirectional, Driven by one device at a time MemoryCPUDiskKeyboard32Control32323232Critical issue: We’re connecting multiple outputs together. Bad Idea!A few (2-3) control lines to each devicePros:• Much fewer wires• Simpler wiring• Expandable• One data port per deviceCons:• More complex electrically• Must manage busExample: Read a value from memory into CPUSeattle Pacific University EE 1210 - Logic System Design Mux-Decoder-9Smoke Happens…OK to connect one output to multiple inputsNot OK to connect outputs together!+5V0+5V1Direct connection from power to ground – smoke!Seattle Pacific University EE 1210 - Logic System Design Mux-Decoder-10Tri-State InverterInOutEn=1InOutEn=0InOutEnHigh-Impedance(Hi-Z) stateModify an inverter…Tri-state InverterOut 5V0VInEnable En Out0 Z1 In’Seattle Pacific University EE 1210 - Logic System Design Mux-Decoder-11Using tri-state gatesGoal: Connect three selectable inputs to a common outputWhenever a select signal is asserted,that input is connected to the outputMust make sure that there is always exactly one driver turned on!in0sel0in1sel1in2sel2outSeattle Pacific University EE 1210 - Logic System Design Mux-Decoder-12DemultiplexersDemultiplexer: One data input, n control inputs, 2n outputs1:2 Demultiplexer:O0 = G • S; O1 = G • SGSO0O1GSO0O1Control inputs (called selects) - Binary index of output to which the input is connectedData input usually called “enable” (‘G’ or ‘E’)Seattle Pacific University EE 1210 - Logic System Design Mux-Decoder-13Larger Demultiplexers/Decoders1:4 Demultiplexer1:8 DemultiplexerO0 = G • S1 • S0O1 = G • S1 • S0O2 = G • S1 • S0O3 = G • S1 • S0O0 = G • S2 • S1 • S0O1 = G • S2 • S1 • S0O2 = G • S2 • S1 • S0O3 = G • S2 • S1 • S0O4 = G • S2 • S1 • S0O5 = G • S2 • S1 • S0O6 = G • S2 • S1 • S0O7 = G • S2 • S1 • S0GS1 S0O0O1O2O3GS2 S1 S0O0O1O2O3O4O5O6O72:4 Decoder3:8 DecoderIf we view the ‘G’ signal as an enable, then a demultiplexer simply decodes the binary select signal into a unary output signal  DecoderDecoder: • Enable=0 all outputs are 0• Enable=1 output is unary representation of binary select inputSeattle Pacific University EE 1210 - Logic System Design Mux-Decoder-14Decoders In VHDLLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY Decoder2to4 ISPORT( s : IN STD_LOGIC_VECTOR(1 downto 0); en : IN STD_LOGIC; y : OUT STD_LOGIC_VECTOR(3 downto 0)); END Decoder2to4;ARCHITECTURE logicfunc OF Decoder2to4 ISBEGINPROCESS(s,en)BEGINIF (en=‘1’) THENCASE (s) IS WHEN “00” => y <= “0001”; WHEN “01” => y <= “0010”; WHEN “10” => y <= “0100”; WHEN “11” => y <= “1000”; WHEN OTHERS => y <= “0000”;END CASE;ELSE y <= “0000”;END IF;END PROCESS;END logicfunc;Sensitive to changes in s or enOnly consider when en = ‘1’If en = ‘0’, then output