Multiplexers A digital n to 1 switch is called a multiplexer or a selector I0 2 1 Multiplexor I1 Z S I0 S I1 S 0 S 1 Two alternative forms for a 2 1 Mux Truth Table Z S 0 1 S Z I0 I1 Functional form Logical form Seattle Pacific University EE 1210 Logic System Design I1 0 0 0 0 1 1 1 1 I0 0 0 1 1 0 0 1 1 S 0 1 0 1 0 1 0 1 Z 0 0 1 0 0 1 1 1 Mux Decoder 1 Multiplexers I0 2 1 mux I1 Z Z SI 0 SI1 I0 I1 I2 I3 S 4 1 mux S1 I0 I1 I2 I3 I4 I5 I6 I7 8 1 mux S2 S1 Z Z Z S1S0I 0 S1S0I1 S1S0I 2 S1S0I 3 S0 Z S2 S1S0I 0 S2 S1S0I1 S2 S1S0I 2 S2 S1S0I 3 S2 S1S0I 4 S2 S1S0I 5 S2 S1S0I 6 S2 S1S0I 7 S0 Seattle Pacific University EE 1210 Logic System Design Mux Decoder 2 VHDL Muxes LIBRARY ieee USE ieee std logic 1164 all ENTITY mux4to1 IS PORT data IN sel IN z OUT END mux4to1 Remember the IEEE library STD LOGIC VECTOR 3 downto 0 STD LOGIC VECTOR 1 downto 0 STD LOGIC Inputs data 3 0 sel 1 0 Output Z ARCHITECTURE behavior OF mux4to1 IS BEGIN PROCESS data sel If Data or Sel change output Z can change BEGIN Set up as a CASE statement CASE sel IS WHEN 00 z data 0 WHEN 01 z data 1 WHEN 10 z data 2 WHEN 11 z data 3 WHEN others z 0 WHEN OTHERS Use this even if END CASE there aren t any others END PROCESS END behavior Seattle Pacific University EE 1210 Logic System Design Mux Decoder 3 Cascading Muxes Large multiplexers can be implemented by cascaded smaller muxes I0 I1 I2 I3 I4 I5 I6 I7 0 4 1 1 mux 2 3 S1 S0 0 4 1 1 mux 2 3 S1 S0 S1 S0 Control signals S1 and S0 simultaneously choose one of I0 I3 and I4 I7 8 1 mux 0 2 1 mux 1 S Z Control signal S2 chooses which of the upper or lower MUX s output to gate to Z I0 I1 0 1 S S0 I2 I3 S2 Alternative 8 1 Mux Implementation 0 1 S 0 S0 2 I4 0 I5 1 S S0 I6 0 I7 1 S 1 Z 3 S 1 S2 S0 S1 S0 Seattle Pacific University EE 1210 Logic System Design Mux Decoder 4 Using Muxes as logic blocks 2n 1 1 multiplexer can implement any function of n variables n 1 control variables remaining variable is a data input to the mux F C B A m0 m2 m6 m7 C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 F 1 0 1 0 0 0 1 1 Seattle Pacific University 1 0 1 0 0 0 1 1 0 1 2 3 4 5 6 7 8 1 MUX F 1 Lookup Table S2 S1 S0 C B A 0 1 0 EE 1210 Logic System Design Mux Decoder 5 Optimized LUTs F C B A m3 m4 m6 m7 CB 00 F 0 CB 01 F A CB 10 F A CB 11 F 1 C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 F 0 0 0 1 1 0 1 1 0 A A 0 A A 1 0 1 2 3 F 4 1 MUX S1 C S0 B 1 We can fit a function of n variables into a 2n 1 1 mux by using this trick note may require one inverter Seattle Pacific University EE 1210 Logic System Design Mux Decoder 6 Using a multiplexor as a switch Consider a computer system with CPU memory I O devices etc Each one needs to be able to communicate with the others Memory CPU Disk Keyboard Seattle Pacific University Pros Conceptually simple 32 32 32 32 4 1 x 32bit Mux 32 00 Control Cons Lots of wires Each device needs separate output and input ports 32 bit mux is a large device Example Read a value from memory into CPU EE 1210 Logic System Design Mux Decoder 7 Using a Bus 32 A few 2 3 control lines to each device Memory CPU 32 32 Control Disk Keyboard Critical issue We re connecting multiple outputs together Bad Idea Seattle Pacific University 32 32 Bus Bidirectional Driven by one device at a time Pros Much fewer wires Simpler wiring Expandable One data port per device Cons More complex electrically Must manage bus Example Read a value from memory into CPU EE 1210 Logic System Design Mux Decoder 8 Smoke Happens 5V 5V OK to connect one output to multiple inputs 1 0 Not OK to connect outputs together Direct connection from power to ground smoke Seattle Pacific University EE 1210 Logic System Design Mux Decoder 9 Tri State Inverter 5V In Out En 1 In Out Enable In Out High Impedance Hi Z state En 0 0V Modify an inverter Seattle Pacific University In Out En Out En 0 Z Tri state Inverter 1 In EE 1210 Logic System Design Mux Decoder 10 Using tri state gates Goal Connect three selectable inputs to a common output in0 sel0 in1 Whenever a select signal is asserted that input is connected to the output sel1 in2 sel2 out Must make sure that there is always exactly one driver turned on Seattle Pacific University EE 1210 Logic System Design Mux Decoder 11 Demultiplexers Demultiplexer One data input n control inputs 2n outputs Control inputs called selects Binary index of output to which the input is connected Data input usually called enable G or E 1 2 Demultiplexer G G S O0 O1 O0 O1 O0 G S O1 G S S Seattle Pacific University EE 1210 Logic System Design Mux Decoder 12 Larger Demultiplexers Decoders O0 O1 O2 G 3 S1 SO 0 1 8 Demultiplexer 3 8 Decoder O0 G S2 S1 S0 1 4 Demultiplexer 2 4 Decoder O1 G S2 S1 S0 O2 G S2 S1 S0 O 0 G S 1 S0 O3 G S2 S1 S0 O 1 G S 1 S0 O4 G S2 S1 S0 O 2 G S 1 S0 O5 G S2 S1 S0 O 3 G S 1 S0 O6 G S2 S1 S0 O 7 G S 2 S1 S 0 Seattle Pacific University O0 O1 O2 O3 G O4 O5 O6 S2 S1 SO 07 If we view the G signal as an enable then a demultiplexer simply decodes the binary select signal into a unary output signal Decoder Decoder Enable 0 all outputs are 0 Enable 1 output is unary representation of binary select input EE 1210 Logic System Design Mux Decoder 13 Decoders In VHDL LIBRARY ieee USE ieee std logic 1164 all ENTITY …