Edge triggering D The carrot symbol means edge triggered Q In a positive edge triggered D FlipFlop the output looks at the input only during the instant that the clock changes from low to high clk Clock D Q Edge triggered D Flip flop Every rising edge output is set to the input Seattle Pacific University EE 1210 Logic System Design FlipFlops 1 Negative Edge triggering D Q In a negative edge triggered D FlipFlop the output looks at the input only on the falling edge of the clock clk Clock D Q Negative Edge triggered D Flip flop Every falling edge output is set to the input Seattle Pacific University EE 1210 Logic System Design FlipFlops 2 Triggering on an Edge We want to briefly enable the FlipFlop whenever we find a rising edge D Q en clock Rising Edge Detect clock en edge clock clock edge d d Edge detection using the time delay through an inverter Seattle Pacific University edge In reality this will be delayed by the AND gate EE 1210 Logic System Design FlipFlops 3 D Latch and FF states D Q en D En Level sensitive gated D latch D En D En Q 1 Q 0 D En D Clk D Q Edge triggered D FF D Clk D Clk Q 1 Q 0 D Clk clk D Edge triggered D FF with clock omitted Seattle Pacific University D D Q 1 Q 0 D EE 1210 Logic System Design FlipFlops 4 VHDL for D FlipFlops LIBRARY ieee USE ieee std logic 1164 all ENTITY DFF IS PORT D IN STD LOGIC CLK IN STD LOGIC Q INOUT STD LOGIC END DFF D Q Inputs D and CLK Output Q PROCESS list State of latch can change due to a change in any of these values ARCHITECTURE behavior OF DFF IS Continuously monitors CLK but not BEGIN D Q only changes on CLK edge PROCESS CLK BEGIN IF RISING EDGE CLK THEN Q D Wait until the clock has a rising edge END IF END PROCESS Q only changes on rising edge END behavior Seattle Pacific University EE 1210 Logic System Design FlipFlops 5 J K Flip Flops We want to eliminate the forbidden state of the R S Latch when R and S are both 1 Idea Q Q are always different Use them to control the input K J Jt Kt Qt Qt 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 Seattle Pacific University Hold Reset R Q Q S Q clk Q J K act just like Set and Reset except When they re both 1 we get a toggle Set Toggle EE 1210 Logic System Design FlipFlops 6 VHDL for J K FlipFlops LIBRARY ieee USE ieee std logic 1164 all J Q Inputs J K and CLK Output Q and Q ENTITY JKFF IS K Q PORT J K IN STD LOGIC CLK IN STD LOGIC Q INOUT STD LOGIC QB OUT STD LOGIC END JKFF ARCHITECTURE behavior OF JKFF IS BEGIN Continuously monitors CLK but not J PROCESS CLK or K Q only changes on CLK edge BEGIN IF RISING EDGE CLK THEN IF J 1 AND K 0 THEN Q 1 ELSIF K 1 AND J 0 THEN Q 0 ELSIF J 1 AND K 1 THEN Q NOT Q ELSE Q Q END IF END IF On clock edge define outputs for all QB NOT Q possible inputs END PROCESS END behavior Seattle Pacific University EE 1210 Logic System Design FlipFlops 7 Toggle Flip Flops Build a flip flop that toggles its state on each clock edge when it is enabled T is the enable Q is the Q output after the clock changes Q T Q T J K Q Q Q Q clk T 0 0 1 1 Q 0 1 0 1 Q 0 1 1 0 T D Q clk Clock T Q Seattle Pacific University EE 1210 Logic System Design FlipFlops 8 Q Asynchronous Presets and Clears Clear forces the output low regardless of the other inputs Preset forces the output high regardless of the other inputs D en R Q S Q Ordinary level sensitive D latch preset D en preset Preset Force S 1 R 0 R Q S Q preset D en clear Clear Force S 0 R 1 clear R Q S Q preset Asynchronous doesn t matter whether clock is high or low Seattle Pacific University EE 1210 Logic System Design FlipFlops 9 Racing the clock D D Q Q Real signals don t change instantly Clk Clk D D is changing during the rising edge of Clk Is a 1 or 0 clocked in Seattle Pacific University D is changing right after the rising edge of Clk Is a 1 or 0 clocked in EE 1210 Logic System Design FlipFlops 10 Setup and Hold Times D D Q Q Clk Setup Time How long a signal must be stable preceding the clock edge Hold Time How long a signal must be stable after the clock edge setup hold time time Clk D Setup Pass Hold Pass Seattle Pacific University Setup Fail Hold Pass Setup Pass Hold Fail EE 1210 Logic System Design Setup Fail Hold Fail FlipFlops 11 Setup and Hold times Flip Flops 74LS74 Positive Edge Triggered D Flipflop 20ns 5ns 20ns 5ns Clk D Q 23 13ns 40 25ns Setup time 20ns Hold time 5ns Propagation delays Low to High 23 ns max 13 ns typ High to Low 40 ns max 25 ns typ Seattle Pacific University EE 1210 Logic System Design FlipFlops 12