Edge-triggeringNegative Edge-triggeringTriggering on an EdgeD Latch and FF statesVHDL for D FlipFlopsJ-K Flip-FlopsVHDL for J-K FlipFlopsToggle Flip-FlopsAsynchronous Presets and ClearsRacing the clockSetup and Hold TimesSetup and Hold times: Flip FlopsSeattle Pacific University EE 1210 - Logic System Design FlipFlops-1Edge-triggeringIn a positive edge-triggered D Flip-Flop, the output looks at the input only during the instant that the clock changes from low to high.ClockQDD QclkEdge-triggered D Flip-flop: Every rising edge, output is set to the inputThe “carrot”symbol meansedge-triggeredSeattle Pacific University EE 1210 - Logic System Design FlipFlops-2Negative Edge-triggeringIn a negative edge-triggered D Flip-Flop, the output looks at the input only on the falling edge of the clock.DD QclkQClockNegative Edge-triggered D Flip-flop: Every falling edge, output is set to the inputSeattle Pacific University EE 1210 - Logic System Design FlipFlops-3Triggering on an EdgeWe want to briefly enable the FlipFlop whenever we find a rising edgeD QenclockenRisingEdgeDetectclockedgeclockedgedclockdedgeEdge detection using the time delay through an inverterIn reality, this will be delayed by the AND gateSeattle Pacific University EE 1210 - Logic System Design FlipFlops-4D Latch and FF statesD QenDD’D’DQ=0Q=1Edge-triggered D-FF with clock omittedD QclkD•Clk↑D’•Clk↑D’+(Clk↑)’D+(Clk↑)’Q=0Q=1D•EnD’•EnD’+En’D+En’Q=0Q=1Edge-triggered D-FFLevel-sensitive (gated) D-latchSeattle Pacific University EE 1210 - Logic System Design FlipFlops-5VHDL for D FlipFlopsLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY DFF ISPORT( D : IN STD_LOGIC; CLK : IN STD_LOGIC; Q : INOUT STD_LOGIC); END DFF;ARCHITECTURE behavior OF DFF ISBEGINPROCESS(CLK)BEGINIF RISING_EDGE(CLK)THEN Q <= D; END IF;END PROCESS;END behavior;Inputs: D and CLKOutput: QPROCESS list  State of latch can change due to a change in any of these valuesWait until the clock has a rising edgeContinuously monitors CLK, but not D (Q only changes on CLK edge)D QQ only changes on rising edgeSeattle Pacific University EE 1210 - Logic System Design FlipFlops-6J-K Flip-FlopsWe want to eliminate the forbidden state of the R-S Latch (when R and S are both 1).Idea: Q, Q’ are always different. Use them to control the input.J, K act just like Set and Reset, except: When they’re both 1, we get a toggle. Jt Kt Qt Qt+1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0HoldResetSetToggleRSQQJKQQclkSeattle Pacific University EE 1210 - Logic System Design FlipFlops-7VHDL for J-K FlipFlopsLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY JKFF ISPORT( J,K : IN STD_LOGIC; CLK : IN STD_LOGIC; Q: INOUT STD_LOGIC; QB: OUT STD_LOGIC); END JKFF;ARCHITECTURE behavior OF JKFF ISBEGINPROCESS(CLK)BEGIN IF RISING_EDGE(CLK)THEN IF (J=‘1’ AND K=‘0’) THEN Q <=‘1’; ELSIF (K=‘1’ AND J=‘0’) THEN Q <=‘0’; ELSIF (J=‘1’ AND K=‘1’) THEN Q <= NOT(Q); ELSE Q <= Q; END IF; END IF;QB <= NOT(Q);END PROCESS;END behavior;Inputs: J,K and CLKOutput: Q and Q’Continuously monitors CLK, but not J or K (Q only changes on CLK edge)JKQQOn clock edge, define outputs for all possible inputsSeattle Pacific University EE 1210 - Logic System Design FlipFlops-8Toggle Flip-FlopsBuild a flip-flop that toggles its state on each clock edge whenit is enabled (T is the enable).TQQT Q Q+0 0 00 1 11 0 11 1 0D QclkTQClockTQ+ is the Q output after the clock changesQJ QQKTclkQQSeattle Pacific University EE 1210 - Logic System Design FlipFlops-9Asynchronous Presets and ClearsClear forces the output low regardless of the other inputs.Preset forces the output high regardless of the other inputs.Asynchronous - doesn’t matter whether clock is high or lowRSQQenDOrdinary level-sensitive D-latchRSQQenDpresetpresetPreset - Force S=1, R=0Clear - Force S=0, R=1RSQQenDpresetpresetclearclearSeattle Pacific University EE 1210 - Logic System Design FlipFlops-10Racing the clockClkD QClkD QReal signals don’t change instantlyDD is changing during the rising edge of Clk. Is a ‘1’ or ‘0’ clocked in?D is changing right after the rising edge of Clk. Is a ‘1’ or ‘0’ clocked in?Seattle Pacific University EE 1210 - Logic System Design FlipFlops-11Setup and Hold TimesSetup Time: How long a signal must be stable preceding the clock edgeClkDsetuptimeholdtimeD QClkD QHold Time: How long a signal must be stable after the clock edgeSetup: PassHold: PassSetup: FailHold: PassSetup: PassHold: FailSetup: FailHold: FailSeattle Pacific University EE 1210 - Logic System Design FlipFlops-12Setup and Hold times: Flip Flops74LS74 PositiveEdge TriggeredD Flipflop• Setup time – 20ns• Hold time – 5ns• Propagation delays - Low to High – 23 ns max, 13 ns typ - High to Low – 40 ns max, 25 ns typDClk20ns 5ns 20ns 5nsQ23/13ns