Implementing Sums of Products A B C D We find And Or structures like this all of the time Z E F A B C D Z 2 x 2 input And Or Invert A B C D E F Z 3 x 2 input And Or Invert Although wiring is simpler part selection is now harder Seattle Pacific University EE 1210 Logic System Design Programmable 1 Programmed Array Logic PAL C B A Fusable links Links may be blown Once blown they are permanently open Fusable links F1 12V Current Complex wiring is replaced with programming F2 PALs support multiple functions of the same inputs C C B B A A Seattle Pacific University EE 1210 Logic System Design Programmable 2 PAL Example C B A Program F1 A B A C A B Blow all unused links F1 A C A BC Program F2 A BC F2 Leave unused product terms alone AA BB CC 0 C C B B A A Seattle Pacific University EE 1210 Logic System Design Programmable 3 Schematic Representation of PALs x s mark Connections Fuses are not blown D C B A DC D C F1 DC D C BA B A BA B A DA CB F2 DA CB D C BA D C BA 0 Seattle Pacific University EE 1210 Logic System Design Programmable 4 The Way Things Are Real PALs Tristate Buffer 2 Input pin I O pin 4 Vcc 3 Input pin GND Output Inversion Ctrl Seattle Pacific University EE 1210 Logic System Design Programmable 5 A More General Idea Programmed Array Logic Programmable Logic Array A PAL has limits on the arrangement of its sum ofproducts groupings Seattle Pacific University A PLA has complete flexibility of its sum ofproducts groupings EE 1210 Logic System Design Programmable 6 Sharing Product Terms in a PLA D C B A F ABC AD AD G ABC ABC AD H ABC BD J B AD ABC ABC AD AD BD B F Seattle Pacific University G H J EE 1210 Logic System Design Programmable 7 Programming Devices PLAs and PALs are programmed using a special programmer Most devices are erasable Don t use fuses but instead electrical methods of programming Erased by exposing to UV light Seattle Pacific University EE 1210 Logic System Design Programmable 8 Macrocells D Interconnect To Other Macrocells Pad Mux Q Memory Invert Control Output Control Mux Clock Control Global Clock Seattle Pacific University Altera Macrocell EE 1210 Logic System Design Programmable 9 CPLDs Complex Programmable Logic Devices Contain from 10 1000 macrocells Each macrocell is equivalent to around 20 gates Support up to 200 I O pins The key resource in a CPLD is interconnect Tradeoff between space for macrocells and space for interconnect Careful design will limit the connections between macrocells Seattle Pacific University EE 1210 Logic System Design Programmable 10 Electrically Erasable PLDs Conventional PLDs are either One time programmable UV Erasable Must be placed in a programmer to program them EE PLDs can be programmed and erased in place A small four wire connection to a computer is needed Once programmed will retain program indefinitely Never have to take the chip out of its circuit Seattle Pacific University EE 1210 Logic System Design Programmable 11 Field Programmable Gate Arrays FPGAs are based on Look up Tables LUTs A LUT is simply a representation of a truth table Example Three input LUT C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 F 1 0 1 0 0 0 1 1 a b c 1 0 f 1 0 0 0 1 1 LUT The function is programmable any LUT can be programmed to be any function 3 input Look up Table FPGAs are just a whole lot of LUTs with lots of interconnect Seattle Pacific University EE 1210 Logic System Design Programmable 12 FPGA Organization I O1 a b c 0x f 0x 1x 1x 0x 1x 1x 1x LUT a b c x x f x x x x x x LUT I O2 Seattle Pacific University a b c 1x f 1x 0x 1x 1x 0x 1x 0x LUT a b c x x f x x x x x x LUT a b c x x f x x x x x x LUT a b c x x f x x x x x x LUT EE 1210 Logic System Design I O3 I O4 Programmable 13 FPGAs FPGAs are based on SRAM Lose programming when power is turned off Can be programmed by a computer or by a special EPROM Capacity May have up to 10 000 000 gate equivalent Up to 1 200 I O pins Seattle Pacific University EE 1210 Logic System Design Programmable 14