Implementing Sums-of-ProductsProgrammed Array Logic (PAL)PAL ExampleSchematic Representation of PALsThe Way Things Are: Real PALsA More General IdeaSharing Product Terms in a PLAProgramming DevicesMacrocellsCPLDsElectrically Erasable PLDsField Programmable Gate ArraysFPGA OrganizationFPGAsSeattle Pacific University EE 1210 - Logic System Design Programmable-1Implementing Sums-of-ProductsZ ABCDEFWe find And-Or structures like this allof the time.Although wiring is simpler, part selection is now harder…A B C D Z E FA B C D Z 2 x 2-input And-Or-Invert 3 x 2-input And-Or-InvertSeattle Pacific University EE 1210 - Logic System Design Programmable-2Programmed Array Logic (PAL)PALs support multiple functions of the same inputsFusable linksC’C B’ B A’ ACBAF1F2Fusable links – Links may be “blown”. Once blown, they are permanently open.Complex wiring is replaced with programmingCurrent+ -12VSeattle Pacific University EE 1210 - Logic System Design Programmable-3PAL ExampleC’C B’ B A’ ACBAF1F2Program F1=A’B’+A’CBlow all unused linksProgram F2=A’BCLeave unused product terms alone (AA’BB’CC’)A’B’A’CA’BC0Seattle Pacific University EE 1210 - Logic System Design Programmable-4Schematic Representation of PALsF1=DC + D’C’ + BA’ + B’AF2=DA + CB’ + D’C’BAD C BADCD’C’BA’B’ADACB’0D’C’BAx’s mark Connections – Fuses are not blownSeattle Pacific University EE 1210 - Logic System Design Programmable-5The Way Things Are: Real PALs23VccGND4Output Inversion CtrlTristate BufferI/O pinInput pinInput pinSeattle Pacific University EE 1210 - Logic System Design Programmable-6A More General IdeaA PLA has complete flexibility of its sum-of-products groupings.Programmable Logic ArrayA PAL has limits on the arrangement of its sum-of-products groupings.Programmed Array LogicSeattle Pacific University EE 1210 - Logic System Design Programmable-7Sharing Product Terms in a PLAF = ABC + AD + ADG =ABC + ABC + ADH =ABC + BDJ = B + ADB ACDF G H JABCABCADADBDBSeattle Pacific University EE 1210 - Logic System Design Programmable-8Programming Devices•PLAs and PALs are programmed using a special programmer•Most devices are erasable•Don’t use fuses, but instead electrical methods of programming•Erased by exposing to UV lightSeattle Pacific University EE 1210 - Logic System Design Programmable-9MacrocellsMuxClockControlMuxOutputControlGlobalClockAltera MacrocellD QMemoryInterconnectTo OtherMacrocellsInvertControlPadSeattle Pacific University EE 1210 - Logic System Design Programmable-10CPLDs•Complex Programmable Logic Devices•Contain from 10-1000 macrocells•Each macrocell is equivalent to around 20 gates•Support up to 200 I/O pins•The key resource in a CPLD is interconnect•Tradeoff between space for macrocells and space for interconnect•Careful design will limit the connections between macrocellsSeattle Pacific University EE 1210 - Logic System Design Programmable-11Electrically Erasable PLDs•Conventional PLDs are either •One-time programmable•UV Erasable•Must be placed in a programmer to program them•EE PLDs can be programmed and erased in place•A small (four wire) connection to a computer is needed•Once programmed, will retain program indefinitely•Never have to take the chip out of its circuitSeattle Pacific University EE 1210 - Logic System Design Programmable-12Field Programmable Gate ArraysFPGAs are based on Look-up Tables (LUTs)A LUT is simply a representation of a truth table3-input Look-up TableC 0 0 0 0 1 1 1 1B 0 0 1 1 0 0 1 1A 0 1 0 1 0 1 0 1F 1 0 1 0 0 0 1 1FPGAs are just a whole lot of LUTs with lots of interconnectabcf10100011LUTExample: Three-input LUTThe function is programmable – any LUT can be programmed to be any functionSeattle Pacific University EE 1210 - Logic System Design Programmable-13FPGA OrganizationabcfxxxxxxxxLUTabcfxxxxxxxxLUTabcfxxxxxxxxLUTabcfxxxxxxxxLUTabcfxxxxxxxxLUTabcfxxxxxxxxLUTI/O1I/O2I/O3I/O40011011111011010Seattle Pacific University EE 1210 - Logic System Design Programmable-14FPGAs•FPGAs are based on SRAM•Lose programming when power is turned off•Can be programmed by a computer or by a special EPROM•Capacity•May have up to 10,000,000 gate equivalent•Up to 1,200 I/O