The Connection: Truth Tables to FunctionsMinterm ShorthandMinterms of Different SizesSum-of-Products MinimizationProduct-of-Sums from a Truth TableMaxtermsMaxterm ShorthandBoolean operations and gatesNAND/NOR expressionsNAND-only circuitsSum-of-Products Circuits with NANDsProduct-of-Sums Circuits with NORsConverting General Circuits to NANDsSeven-Segment ExampleSeven Segment Truth TableCircuits for Segment a Seattle Pacific University EE 1210 - Logic System Design SOP-POS-1The Connection: Truth Tables to Functionsa b c F0 0 0 00 0 1 10 1 0 10 1 1 11 0 0 01 0 1 11 1 0 11 1 1 0a b c- -a b c- -a b c- -a b c- -a b c- -Function F is true if any ofthese and-terms are true!Condition that a is 0, b is 0, c is 1.ORSum-of-Products formF a b c a b c a b c a b c a b c - -  - -  - -  - -  - -( ) ( ) ( ) ( ) ( ) Seattle Pacific University EE 1210 - Logic System Design SOP-POS-2Minterm ShorthandF a b c a b c a b c a b c a b cF - -  - -  - -  - -  - -( ) ( ) ( ) ( ) ( )( , , , , ) m + m + m + m + m F = 1 2 3 5 6m1 2 3 5 6a b c- -a b c- -a b c- -a b c- -a b c- -a b c- -a b c- -a b c- -= m0= m1= m2= m3= m4= m5= m6= m7Note: Binary orderingA minterm has one literal for each input variable, either in its normal or complemented form.A canonical sum-of-products form of an expression consists only of minterms OR’d togethera b c F0 0 0 00 0 1 10 1 0 10 1 1 11 0 0 01 0 1 11 1 0 11 1 1 0 Seattle Pacific University EE 1210 - Logic System Design SOP-POS-3Minterms of Different SizesTwo variables:a b minterm0 0 a’b’ = m00 1 a’b = m11 0 a b’ = m21 1 a b = m3Three variables:a b c minterm0 0 0 a’b’c’ = m00 0 1 a’b’c = m10 1 0 a’b c’ = m20 1 1 a’b c = m31 0 0 a b’c’ = m41 0 1 a b’c = m51 1 0 a b c’ = m61 1 1 a b c = m7Four variables:a b c d minterm0 0 0 0 a’b’c’d’ = m00 0 0 1 a’b’c’d = m10 0 1 0 a’b’c d’ = m20 0 1 1 a’b’c d = m30 1 0 0 a’b c’d’ = m40 1 0 1 a’b c’d = m50 1 1 0 a’b c d’ = m60 1 1 1 a’b c d = m71 0 0 0 a b’c’d’ = m81 0 0 1 a b’c’d = m91 0 1 0 a b’c d’ = m101 0 1 1 a b’c d = m111 1 0 0 a b c’d’ = m121 1 0 1 a b c’d = m131 1 1 0 a b c d’ = m141 1 1 1 a b c d = m15 Seattle Pacific University EE 1210 - Logic System Design SOP-POS-4Sum-of-Products MinimizationF a b c a b c a b c a b c a b c - -  - -  - -  - -  - -( ) ( ) ( ) ( ) ( )F in canonical sum-of-products form (minterm form):Use algebraic manipulation to make a simpler sum-of-products form)()()()()()( cbacbacbacbacbacbaF ------------Use commutativity to reorder to group similar terms ))(())(())(( cbaabacccbaaF ---Use distributivity to factor out common terms)()()( cbbacbF ---Use x’+x = 1 identityDuplicate term - OKWe will find a better method (K-maps) later… Seattle Pacific University EE 1210 - Logic System Design SOP-POS-5Product-of-Sums from a Truth TableA 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 0 0 1 1 1 1 1 F 1 1 1 0 0 0 0 0 CBACBACBAF Use DeMorgan’s Law to re-express as product-of sumsFind an expressionfor F’ (the complement)Complement both sides…)()()( CBACBACBAFCBACBACBAF----CBACBACBAF  Seattle Pacific University EE 1210 - Logic System Design SOP-POS-6MaxtermsA 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 0 0 1 1 1 1 1 F 1 1 1 0 0 0 0 0 F A B C A B C A B C   -   -  ( ) ( ) ( )•To find a Product-of-Sums form for a truth table•Make one maxterm for each row in which the function is zero•For each maxterm, each variable appears once•In its complemented form if it is one in the row•In its regular form if it is zero in the rowMaxterms Seattle Pacific University EE 1210 - Logic System Design SOP-POS-7Maxterm ShorthandProduct of SumsF in canonical maxterm form:A B C Maxterms A + B + C = M7A + B + C = M6A + B + C = M5A + B + C = M4A + B + C = M3A + B + C = M2A + B + C = M1A + B + C = M00 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1F A B C A B C A B CF M M MF   -   -   - -( ) ( ) ( )0 1 2M(0, 1, 2) Seattle Pacific University EE 1210 - Logic System Design SOP-POS-8Boolean operations and gates•Theorem: Any operation than can be represented by a truth table can be represented in Boolean algebra•All truth tables can be made out of only and, or, and not functions Seattle Pacific University EE 1210 - Logic System Design SOP-POS-9NAND/NOR expressionsAny expression can be made of and ANDs, ORs and NOTsThus, we can make any expression out of NANDs, NORs, and NOTsSo, we can make any expression out of just NANDs and NORsXXnote: NANDs and NORs are easy to build with switchesWe can make ANDs and ORs from NANDs and NORs and NOTsWe can make NOTs out of a single NAND gate Seattle Pacific University EE 1210 - Logic System Design SOP-POS-10NAND-only circuitsUsing DeMorgan’s LawNORs can be made with NANDs!We can make any Boolean expression out of only NAND GatesNANDs can be made out of NORs!We can make any Boolean expression out of only NOR Gates Seattle Pacific University EE 1210 - Logic System Design SOP-POS-11Sum-of-Products Circuits with NANDsIntroduce Double InvertersSum-of-Productsworks well with NANDsDeMorgan’sLaw Seattle Pacific University EE 1210 - Logic System Design SOP-POS-12Product-of-Sums Circuits with NORsIntroduce Double InvertersProduct-of-Sumsworks well with NORsDeMorgan’sLaw Seattle Pacific University EE 1210 - Logic System Design SOP-POS-13Converting General Circuits to NANDsABDCBACDBDIntroduce Double Inverters to make NANDs:Add inverters as needed to maintain correct polarityRepresent inverters with NANDs Seattle Pacific University EE 1210 - Logic System Design SOP-POS-14Seven-Segment ExampleA seven-segment display is used to display numbers abcdefga b c d e fb ca b d e ga b c d gb c f ga c d f ga …