The Grunt Work of Design Many design tasks require a lot of time and effort Forming logic expressions Truth tables Reducing logic complexity Boolean Algebra Making schematics Analyzing logic circuits Design changes require starting over at the beginning Re design Re do logic reduction Re analyze Computers can come to our rescue Computer Aided Design tools CAD Seattle Pacific University EE 1210 Logic System Design CAD VHDL 1 CAD Tools In logic design CAD tools help us in Design Entry Composing a design in a way that is easily understood by computers and people Logic Synthesis Forming logic equations from higher level concepts Reducing the complexity of logic equations Simulation Predicting how the resulting circuit will behave Implementation Building an actual circuit for your logic Seattle Pacific University EE 1210 Logic System Design CAD VHDL 2 Design Entry Designs can be entered in many different forms Schematics D A B C B A C D Truth tables Programming languages Waveforms f x1 AND x2 OR NOT x3 AND x2 g x1 OR x3 AND x2 OR NOT x1 Combinations of all the a a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 F 0 1 1 1 0 1 1 0 above Seattle Pacific University EE 1210 Logic System Design CAD VHDL 3 VHDL VHSIC Hardware Description Language Represents digital signals as variables Major parts ENTITY Describes high level interfaces Inputs and Outputs ARCHITECTURE Describes actual logical function or behavior of circuit Seattle Pacific University EE 1210 Logic System Design CAD VHDL 4 VHDL Entities ENTITY describes high level interface Name of ENTITY note must be same as file name Inputs to sevensegment ENTITY sevensegment IS PORT A B C D IN BIT sa sb sc sd se sf sg OUT BIT END sevensegment End of ENTITY Outputs from sevensegment WARNING Syntax is critical and compiler is unforgiving Seattle Pacific University EE 1210 Logic System Design CAD VHDL 5 VHDL Architectures Architecture describes what to actually implement Should describe each output in terms of inputs D B A B C sa A Describing logical function Name of entity this is part of C D Definition of outputs ARCHITECTURE LogicFunc OF sevensegment IS sa A OR B OR C OR NOT D AND A OR NOT B OR C OR D sb END LogicFunc Function in terms of AND OR NOT NAND NOR XOR XNOR Seattle Pacific University EE 1210 Logic System Design CAD VHDL 6 Synthesis Synthesis Converting various forms of logic representations into better representations Inputs Schematics Truth tables VHDL Waveforms Outputs A single logical description of the entire system in various representation May be optimized according to user specified criteria Smallest form Fastest form etc Synthesis mechanisms Boolean algebra related algorithms Seattle Pacific University EE 1210 Logic System Design CAD VHDL 7 Simulation Simulation predicts how the circuit will perform Functional Simulation Predicts only the logical operation of the circuit Fast Timing Simulation Inputs Predicts the actual timing operation of the circuit Requires knowledge of how the circuit will be implemented A B C T1 T2 Z 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 Seattle Pacific University EE 1210 Logic System Design CAD VHDL 8 Altera CAD Tools CAD tools that include Design entry Synthesis Simulation functional or timing Implementation in Altera PLDs and FPGAs Student version Implementation portion limited to a small variety of Altera PLDs FPGAs Seattle Pacific University EE 1210 Logic System Design CAD VHDL 9 Designing with Altera Quartus 1 Create a new design 2 Input design using various design entry tools Graphical Schematic Truth Tables Waveforms Textual VHDL AHDL 3 Synthesize Design Functional Errors 4 Functional Simulation 5 Synthesize Design for Implementation 6 Timing Simulation Timing wrong 7 Implement in Hardware Seattle Pacific University EE 1210 Logic System Design CAD VHDL 10