The Grunt Work of DesignCAD ToolsDesign EntryVHDLVHDL EntitiesVHDL ArchitecturesSynthesisSimulationAltera CAD ToolsDesigning with Altera Quartus Seattle Pacific University EE 1210 - Logic System Design CAD-VHDL-1The Grunt Work of Design•Many design tasks require a lot of time and effort•Forming logic expressions (Truth tables)•Reducing logic complexity (Boolean Algebra)•Making schematics•Analyzing logic circuits•Design changes require starting over at the beginning•Re-design, Re-do logic reduction, Re-analyze•Computers can come to our rescue!•Computer Aided Design tools - CAD Seattle Pacific University EE 1210 - Logic System Design CAD-VHDL-2CAD Tools•In logic design, CAD tools help us in:•Design Entry•Composing a design in a way that is easily understood by computers and people•Logic Synthesis•Forming logic equations from higher-level concepts•Reducing the complexity of logic equations•Simulation•Predicting how the resulting circuit will behave•Implementation•Building an actual circuit for your logic Seattle Pacific University EE 1210 - Logic System Design CAD-VHDL-3Design Entry•Designs can be entered in many different forms•Schematics•Truth tables•Programming languages•Waveforms•Combinations of all the aboveABCDABCDaa b c F0 0 0 00 0 1 10 1 0 10 1 1 11 0 0 01 0 1 11 1 0 11 1 1 0f<=(x1 AND x2)OR(NOT(x3 AND x2));g<=(x1 OR x3)AND(x2 OR (NOT(x1))) Seattle Pacific University EE 1210 - Logic System Design CAD-VHDL-4VHDL•VHSIC Hardware Description Language•Represents digital signals as variables•Major parts•ENTITY•Describes high-level interfaces•Inputs and Outputs•ARCHITECTURE•Describes actual logical function or behavior of circuit Seattle Pacific University EE 1210 - Logic System Design CAD-VHDL-5VHDL Entities•ENTITY describes high-level interfaceENTITY sevensegment ISPORT (A,B,C,D: IN BIT; sa,sb,sc,sd,se,sf,sg: OUT BIT);END sevensegment;Name of ENTITY (note: must be same as file name)Inputs to sevensegmentOutputs from sevensegmentEnd of ENTITYWARNING: Syntax is critical and compiler is unforgiving Seattle Pacific University EE 1210 - Logic System Design CAD-VHDL-6VHDL Architectures•Architecture describes what to actually implement•Should describe each output in terms of inputsABCDABCDsaARCHITECTURE LogicFunc OF sevensegment ISsa <= (A OR B OR C OR (NOT D)) AND(A OR (NOT B) OR C OR D);sb <= …..END LogicFunc;Describing logical functionName of entity this is part ofDefinition of outputsFunction in terms of AND, OR, NOT, NAND, NOR, XOR, XNOR Seattle Pacific University EE 1210 - Logic System Design CAD-VHDL-7Synthesis•Synthesis – Converting various forms of logic representations into better representations•Inputs – •Schematics, Truth tables, VHDL, Waveforms•Synthesis mechanisms•Boolean algebra, related algorithms•Outputs – •A single logical description of the entire system, in various representation•May be optimized according to user-specified criteria•Smallest form, Fastest form, etc. Seattle Pacific University EE 1210 - Logic System Design CAD-VHDL-8Simulation•Simulation predicts how the circuit will perform•Functional Simulation•Predicts only the logical operation of the circuit•Fast•Timing Simulation•Predicts the actual timing operation of the circuit•Requires knowledge of how the circuit will be implementedABCT1T2Z101010101010Inputs0 0 0 0 1 1 1 10 0 1 1 0 0 1 10 1 0 1 0 1 0 11 1 1 1 0 0 0 00 1 1 1 0 1 1 10 1 1 1 0 0 0 0 Seattle Pacific University EE 1210 - Logic System Design CAD-VHDL-9Altera CAD Tools•CAD tools that include:•Design entry•Synthesis•Simulation (functional or timing)•Implementation (in Altera PLDs and FPGAs)•Student version:•Implementation portion limited to a small variety of Altera PLDs/FPGAs Seattle Pacific University EE 1210 - Logic System Design CAD-VHDL-10Designing with Altera Quartus1. Create a new design2. Input design using various design entry toolsGraphical (Schematic)Textual (VHDL, AHDL)Truth TablesWaveforms3. Synthesize Design (Functional)4. Functional Simulation5. Synthesize Design for Implementation6. Timing Simulation7. Implement in HardwareErrors?Timing