A Strange Counter QA D Q QA DB D Q DC QB D Q QC clk Clock QA 0 0 1 0 0 1 QB 0 1 1 0 1 1 QC 0 1 0 0 1 0 State State 000 000 State State 011 011 Seattle Pacific University State State 110 110 State000 State000 State State 011 011 State State 110 110 EE 1210 Logic System Design CustomCounters 1 A Strange Counter Redrawn Combinational Feedback Logic DA Next State DB DC D Q D Q D Q QA QB Current State Output QC clk Seattle Pacific University EE 1210 Logic System Design CustomCounters 2 A Generalized Synchronous Circuit Next State Current State State FlipFlops Combinational Logic For Next State Comb Logic For Outputs Outputs Clock Clock Outputs may be The state itself Some function of the state The number of possible states is 2n where n is the number of FlipFlops Seattle Pacific University EE 1210 Logic System Design CustomCounters 3 Analyzing a counter DA QB QC DB QAQB DC QB QA DA D Q QA clr DB D Q QB clr DC D Current State QA 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 QC 0 1 0 1 0 1 0 1 FF Inputs DA 0 1 1 1 0 1 1 1 DC 1 0 0 0 1 0 0 0 QA 0 1 1 1 0 1 1 1 QB 1 1 1 1 1 1 0 0 QC 1 0 0 0 1 0 0 0 QAQBQC Q QC 001 000 011 clr reset DB 1 1 1 1 1 1 0 0 Next State clk Seattle Pacific University 010 110 111 100 EE 1210 Logic System Design 101 CustomCounters 4 Custom Counters Step 1 Derive the State Transition Diagram Count sequence 000 011 100 101 010 001 000 Step 2 State Transition Table Current State Next State QA 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 Q C QA 0 0 1 0 0 0 1 1 0 1 1 0 0 X 1 X QB 1 0 0 0 0 1 X X Seattle Pacific University QC 1 0 1 0 1 0 X X 011 000 001 100 010 101 Note the Don t Care conditions EE 1210 Logic System Design CustomCounters 5 Custom Counter Mapping to D FFs Step 3 Choose Flipflop Type for Implementation Figure out FF inputs that will cause appropriate state change Current State Next State QA 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 QC 0 1 0 1 0 1 0 1 QA 0 0 0 1 1 0 X X QB 1 0 0 0 0 1 X X QC 1 0 1 0 1 0 X X FF Inputs DA 0 0 0 1 1 0 X X DB 1 0 0 0 0 1 X X DC 1 0 1 0 1 0 X X For D FF s next state is just the D input Q D Next State Functions with D FF s Seattle Pacific University EE 1210 Logic System Design CustomCounters 6 Custom Counter Finishing Step 4 Make K maps for each flipflop input and find final functions DA C 0 AB A 00 0 01 0 C DB C 0 AB 1 0 1 11 X X 10 1 0 B A DA AC BC DC C 0 AB A 00 1 01 1 00 1 01 0 C 1 0 0 11 X X 10 0 1 DB A B C AC C GND B C B Pre D C A Q Clr A B C A C Pre D Q X X 10 1 0 B Clr GND 0 11 Reset GND 1 0 A C B Pre D Q C Clr DC C Seattle Pacific University EE 1210 Logic System Design CustomCounters 7 Custom Counter Remapping to T FFs Step 3 Choose Flipflop Type for Implementation Figure out FF inputs that will cause appropriate state change Current State Next State QA 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 QC 0 1 0 1 0 1 0 1 QA 0 0 0 1 1 0 X X QB 1 0 0 0 0 1 X X QC 1 0 1 0 1 0 X X FF Inputs TA TB T C 0 1 1 0 0 1 0 1 1 1 1 1 0 0 1 1 1 1 X X X X X X For T FF s we have to look at the current state and the next If the next state is different from the current then we must toggle T 1 Next State Functions with T FF s Seattle Pacific University EE 1210 Logic System Design CustomCounters 8 Finishing with Toggle FFs Step 4 Make K maps for each flipflop input and find final functions TA C 0 AB A 00 0 01 0 C 0 1 X X 10 0 1 TA C A B C 0 AB A 00 1 01 1 11 10 X 1 C 0 AB 1 11 TC TB B A 1 00 1 01 1 1 11 X X 10 0 1 0 TB A C B AC C 1 GND B A B C Pre T Q A Clr Reset GND A C B A C Pre T Q B Clr GND 1 1 C 1 Pre T Q C Clr B X 1 TC 1 Seattle Pacific University EE 1210 Logic System Design CustomCounters 9 VHDL Counters LIBRARY ieee USE ieee std logic 1164 all 000 ENTITY cnt IS 011 A 001 PORT clk IN STD LOGIC B F reset IN STD LOGIC z OUT STD LOGIC VECTOR 2 downto 0 100C E END cnt 010 ARCHITECTURE behavior OF cnt IS D 101 Type state type is A B C D E F SIGNAL state state type BEGIN Declare possible states PROCESS reset clk A F is six states BEGIN if reset 1 then state A z 000 Asynchronous reset to 000 elsif rising edge clk then case state is when A state B z 011 when B state C z 100 when C state D z 101 Here s the counter when D state E z 010 when E state F z 001 when F state A z 000 END CASE end if end process END behavior Seattle Pacific University EE 1210 Logic System Design CustomCounters 10