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A Strange CounterA Strange Counter (Redrawn)A Generalized Synchronous CircuitAnalyzing a counterCustom CountersCustom Counter: Mapping to D FFsCustom Counter: FinishingCustom Counter: Remapping to T FFsFinishing with Toggle FFsVHDL CountersSeattle Pacific University EE 1210 - Logic System Design CustomCounters-1A Strange CounterClockQAQBQCD QclkD QD QQAQBQCDBDCQA+110State 110State 110000State 000State 000011State 011State 011000State000State000011State 011State 011110State 110State 110Seattle Pacific University EE 1210 - Logic System Design CustomCounters-2A Strange Counter (Redrawn)D QclkD QQAQBQCD QCurrentState(Output)CombinationalFeedback LogicNextStateDADBDCSeattle Pacific University EE 1210 - Logic System Design CustomCounters-3A Generalized Synchronous CircuitCombinationalLogicFor Next StateComb.LogicFor OutputsOutputsStateFlipFlopsClockClockCurrentStateNextStateOutputs may be:The state itselfSome function of the stateThe number of possible states is 2n, where n is the number of FlipFlops.Seattle Pacific University EE 1210 - Logic System Design CustomCounters-4Analyzing a counterDA=QB+QCDB=QAQBDC=QB+QAD QD QQAQBQCD QDAclkDBDCclrclrclrreset000011110100QAQBQC101111001001001001011011110110011011011011011011110110111011101001110010100000QC+QB+QA+DCDBDAQCQBQANext StateFF InputsCurrent State001010Seattle Pacific University EE 1210 - Logic System Design CustomCounters-5Custom CountersStep 1: Derive the State Transition DiagramCount sequence: 000, 011, 100, 101, 010, 001,000,…Step 2: State Transition TableNote the Don't Care conditions000011100101010001XXXXXX010101001100000110111011101001110010100000QCQBQANext StateCurrent StateQC+QB+QA+Seattle Pacific University EE 1210 - Logic System Design CustomCounters-6Custom Counter: Mapping to D FFsNext State Functions with D FF’sStep 3: Choose Flipflop Type for Implementation Figure out FF inputs that will cause appropriate state changeFor D FF’s next state is just the D input: Q+  DXXXXXX010101001100000110111011101001110010100000QCQBQAFF InputsNext StateCurrent StateQC+QB+QA+DCDBDAXXXXXX010101001100000110Seattle Pacific University EE 1210 - Logic System Design CustomCounters-7Custom Counter: FinishingDB=A’B’C’ + ACDC= C’DA=AC’ + BCStep 4: Make K-maps for each flipflop input and find final functionsD QPreClrCC’GNDD QPreClrBGNDB’ACA’C’D QPreClrAGNDCC’ABReset1 0 DAABC00 01 11 10 0 1 BC A 0 0 0 X X 1 0 1 DBABC00 01 11 10 0 1 BC A 0 1 0 X X 0 0 1 DCABC00 01 11 10 0 1 BC A 0 0 1X X 1Seattle Pacific University EE 1210 - Logic System Design CustomCounters-8Custom Counter: Remapping to T FFsNext State Functions with T FF’sStep 3: Choose Flipflop Type for Implementation Figure out FF inputs that will cause appropriate state changeFor T FF’s, we have to look at the current state and the next.If the next state is different from the current, then we must toggle (T=1).XXXXXX111100111110100110111011101001110010100000QCQBQAFF InputsNext StateCurrent StateQC+QB+QA+TCTBTAXXXXXX010101001100000110Seattle Pacific University EE 1210 - Logic System Design CustomCounters-9Finishing with Toggle FFsTB= A’C’ + B + ACTC=1TA=C(A+B)Step 4: Make K-maps for each flipflop input and find final functionsT QPreClrC‘1’GNDT QPreClrAGNDBACT QPreClrBGNDBACA’C’1 0 TAABC00 01 11 10 0 1 BC A 0 1 0 X X 0 1 1 TBABC00 01 11 10 0 1 BC A 0 1 1 X X 0 1 1 TCABC00 01 11 10 0 1 BC A 1 1 1X X 1 ResetSeattle Pacific University EE 1210 - Logic System Design CustomCounters-10VHDL CountersLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY cnt ISPORT(clk: IN STD_LOGIC;reset: IN STD_LOGIC;z: OUT STD_LOGIC_VECTOR(2 downto 0));END cnt;ARCHITECTURE behavior OF cnt ISType state_type is (A,B,C,D,E,F);SIGNAL state: state_type;BEGINPROCESS(reset,clk)BEGINif (reset=‘1’) thenstate <= A;z <=“000”;elsif (rising_edge(clk))thencase state iswhen A=> state <= B; z <= "011";when B=> state <= C; z <= “100";when C=> state <= D; z <= "101";when D=> state <= E; z <= “010";when E=> state <= F; z <= “001";when F=> state <= A; z <= "000";END CASE;end if;end process;END behavior;Declare possible states (A-F is six states)Asynchronous reset to 000Here’s the


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SPU EE 1210 - A Strange Counter

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