SPU EE 1210 - Quartus II Tutorial – Building and Simulating a Logic Circuit Using VHDL

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Quartus II Tutorial Building and simulating a logic circuit using VHDL Kevin Bolding Seattle Pacific University Introduction Quartus II is a powerful tool for entering editing simulating and building digital circuits In this tutorial you will learn how to enter a VHDL design in Quartus II edit it compile it and simulate it Getting started Before starting Quartus II Before starting your project you should first create a folder File New Folder from any Explorer Window to store your circuit and simulation information in There are different choices to make depending on whether you are using a school computer or your home computer Home computer You may make a folder wherever you like to store your data Use Windows to create this directory Lab computer Use your netstore drive N Create a directory on this drive such as N alterawork tutorial1 At this point you now have a folder in which to keep work for this tutorial Starting up Quartus II Start up Quartus II by clicking on the Quartus II link from the Start Menu On lab machines this is in Start Engineering Sciences Altera Quartus II ver Web Edition A getting started window will appear Choose Create a New Project Next you ll be asked to pick a project directory and name your project 1 Select the directory you set up in the beginning or make a new one now Give your project a name such as circuit2 The top level entry should have the same name Click Next 2 Add files You have no existing files so just click Next 3 Family and Device Select the chip used in the Altera DE1 boards Cyclone II 2C20F484C7 Click Next 4 EDA Tools Settings Just click Next 5 Summary Look over the settings and click Finish At this point the main Quartus II environment should be open You should see the project name you entered circuit1 listed in the upper left under Entity Building a circuit The next step is to describe a circuit using the Quartus II editor For this tutorial we will use a graphical logic gate drawing to describe our circuit Opening up a new VHDL File Altera uses the extension VHD for schematic block diagram files We will create our first VHDL design by using the Text Editor built into Quartus II To define a new VHDL file 1 Select File New 2 Select Design Files VHDL File 3 Click on OK This creates a new file with a name like VHDL1 VHD 4 Give the file a name by selecting File Save or clicking on the disk tool button 5 Type the name circuit2 in the dialog box WARNING the top level VHDL file this one must be named the same as your project name 6 Click on Save The file is now named circuit2 vhd At this point you now have within the Quartus II window a window for you to enter your VHDL code You may minimize or maximize this window if you wish Also notice that there is a tab for this internal window right now it is the only tab but later when you have more files you can switch between files by clicking on the tab Entering your VHDL Design You may enter your VHDL design by simply typing in the code We want to build a circuit that implements the function Z A B ABC BC Remember there are two major parts to a VHDL design the ENTITY which describes the input output portions of the circuit and the ARCHITECTURE which gives the details for the circuit Begin with the ENTITY which should give the following information Entity name circuit2 this must match the filename of the VHD file and the project name Inputs A B C Outputs Z Now enter the ARCHITECTURE which should specify the logic function Z A B ABC BC Remember to refer to circuit2 in the of clause Compiling your circuit Now that you ve drawn your first circuit it is time to compile it Compiling is the process in which the computer reads the diagram you have drawn and converts it to its own internal form so it can simulate and build the circuit for you The compiler will also check your diagram for any obvious errors Using the compiler tool Bring up the compiler and compile your project by the following method 1 Select the compiler tool by choosing Processing Start Compilation or by clicking on the play tool button A compiler window should open up 2 A Flow Summary window should show up and various indicators of progress in the development environment will show up You ll see lots of information messages in the lower window If all goes well you should see one or more successful messages To see your VHDL file again click on the tab for it at the top of the window Finding and fixing errors Of course you did this tutorial perfectly so you had no errors Let s make some errors and see what happens 1 Edit your VHDL file to remove the parenthesis after the AND B in the logic statement see below 2 Now save the VHDL file and start up the compiler again press start on the compiler 3 Notice that a window pops up stating that your project has errors and they re listed at the bottom of the screen Click OK on the warning window so it will go away 4 Look at the Messages window it should list three errors as shown below The first error message says that a parenthesis is missing 5 To trace this error down double click on the first error message Notice that the VHDL window pops up and the offending statement is highlighted 6 Fix your error and save your file Printing your VHDL file Use the Print Preview function to make sure that your file will print properly before clicking on the print button Simulating your circuit At this point you have a valid circuit entered into Quartus II It is time to simulate it to check its operation To do this we ll have to set up a simulator file and define inputs We can then check the outputs to confirm that this circuit does what we designed it to do Making a simulation file We ll start by building a simulation file 1 Select File New and select Vector Waveform File A new window will open with a simulator file in it Save this file as circuit1 vwf 2 Zoom out to see all 1000ns Use the magnifying glass button remember left click zooms in right click zooms out to do this Selecting nodes to simulate The first step in simulating your circuit is to select which nodes to simulate and display For our simple circuit we ll choose the inputs and outputs A B C and Z 1 Right click in the left portion of the simulator window under Name and Value Select Insert Insert Node or Bus see below A window will pop up 2 Click Node Finder A new window will pop up 3 Make sure that the middle drop down box reads Pins all Click …


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SPU EE 1210 - Quartus II Tutorial – Building and Simulating a Logic Circuit Using VHDL

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