Moore MachinesMealy MachinesMealy FSM DiagramsMealy FSM Diagrams - EfficiencyMealy Gumball Machine – Table FormMealy Gumball Machine ImplementationPattern Matcher – Moore and MealyPattern Matcher - A Better Way?VHDL Pattern Matcher - MooreVHDL Pattern Matcher - MealyReview of FSM Design ProcessComplex CounterSlide 13Digital Combination LockAn assumptionSlide 16Party MachineParty Machine ImplementationParty Machine - AlternativeVCR controllerAirlock controllerCombo Lock #2Washing MachineTennis ScorerSeattle Pacific University EE 1210 - Logic System Design MooreMealy-1Moore MachinesCombinationalLogicFor Next StateComb.LogicFor OutputsOutputsStateFlipFlopsClockClockCurrent StateNext StateInputsA Moore FSM –Outputs are a function of ONLY the current stateQCurrent StateOpenOutput0¢ 05¢ 010¢ 015+¢ 10¢5¢10¢DDNNN+DReset15+¢[open=1]N’D’N’D’N’D’N’D’DNSeattle Pacific University EE 1210 - Logic System Design MooreMealy-2Mealy MachinesCombinationalLogicFor Next StateComb.LogicFor OutputsOutputsStateFlipFlopsClockClockCurrent StateNext StateInputsA Mealy FSM –Outputs are a function of the current state and inputsWARNING – Outputs are no longer synchronized with clockSeattle Pacific University EE 1210 - Logic System Design MooreMealy-3Mealy FSM DiagramsIn a Mealy FSM, the outputs depend on the current state and the inputsWe can’t just label the states with the outputs anymore.0¢5¢10¢D/0D/1N/0N/0N+D/1Reset15+¢N’D’/0N’D’/0N’D’/0N’D’/0D/0N/0Outputs are associated with ARCS (transitions between states)Arc Labeling:Input(s)/Output(s)Seattle Pacific University EE 1210 - Logic System Design MooreMealy-4Mealy FSM Diagrams - EfficiencyExamine the 15+¢ state:We spend almost no time in it – it’s purpose was to output the signal OPEN0¢5¢10¢D/0D/1N/0N/0N+D/1Reset15+¢N’D’/0N’D’/0N’D’/0N’D’/0D/0N/0But, in Mealy FSMs, we don’t use states for outputs  The 15+¢ state is not needed!0¢5¢10¢D/0N/0N/0ResetN’D’/0N’D’/0N’D’/0D/1N+D/10¢5¢10¢DDNNN+DReset15+¢[open=1]N’D’N’D’N’D’N’D’DNMoore MealyEfficient MealySeattle Pacific University EE 1210 - Logic System Design MooreMealy-5Mealy Gumball Machine – Table Form0¢5¢10¢D/0N/0N/0ResetN’D’/0N’D’/0N’D’/0D/1N+D/1Efficient MealyPresent StateInputs Next State OutputQ1Q0D N Q1+Q0+Open0 0 0 0 0 0 00 0 0 1 0 1 00 0 1 0 1 0 00 0 1 1 X X X0 1 0 0 0 1 00 1 0 1 1 0 00 1 1 0 0 0 10 1 1 1 X X X1 0 0 0 1 0 01 0 0 1 0 0 11 0 1 0 0 0 11 0 1 1 X X X1 1 0 0 X X X1 1 0 1 X X X1 1 1 0 X X X1 1 1 1 X X X000110Only using three states – State 11 is all don’t caresNotice that Output is now a function of state and inputsAssign numbers to statesSeattle Pacific University EE 1210 - Logic System Design MooreMealy-6Mealy Gumball Machine ImplementationQ1Q0DN00 01 11 10 00 01 11 10 Q1 Q0D ND10 xxx x x0 0 1 x 0 0 1 0 x 1 Q1Q0DN00 01 11 10 00 01 11 10 Q1 Q0D ND01 xxx x x0 1 0 x 0 1 0 1 x 0 D1= DQ1’Q0’ + NQ0 + D’N’Q1D2= NQ0’ + D’N’Q0 + DQ1Open = DQ0 + NQ1 + DQ1Note that the output is a function of the state and the inputsIf we chose D FF’s, we don’t have to convert Q’s to FF inputsQ1Q0DN00 01 11 10 00 01 11 10 Q1 Q0D NOpen1 xxx x x0 1 0 x 1 0 0 0 x 0Seattle Pacific University EE 1210 - Logic System Design MooreMealy-7Pattern Matcher – Moore and MealyMachine that outputs 1 when last three inputs were “010”, unless “100” has ever been seenS0 S1 S2 S4 S5 S6 (0+1)/0Reset/01/00/10/00/00/01/0...100...01...00/0...11/0...101/01/0MooreMealyS0 [0]S1 [0]S2 [0]S3 [1]S4 [0]S5 [0]S6 [0]0+1Reset10 0001...010...10001...01...00...11...1011The purpose of state S3 is to output ‘1’ – can we get rid of it?Seattle Pacific University EE 1210 - Logic System Design MooreMealy-8Pattern Matcher - A Better Way?Q2Q1Q0 are the last three bits shifted in (in that order)Outputs Z=1 if sees 010Shift RegisterQ2Q1Q0Shift inEnXQ2Q1Q0clk Q2Q1Q0Z Q2Q1Q0If last three bits were 100, enable is turned off and all shifting stopsIf last three bits were 010, output 1 unless 100 has ever been seen.Seattle Pacific University EE 1210 - Logic System Design MooreMealy-9VHDL Pattern Matcher - MooreLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY patternmatch ISPORT(clk: IN STD_LOGIC;reset: IN STD_LOGIC;x: IN STD_LOGIC;z: OUT STD_LOGIC);END patternmatch;ARCHITECTURE behavior OF patternmatch IS Type state_type is (S0,S1,S2,S3,S4,S5,S6); SIGNAL state: state_type;BEGINPROCESS(reset,clk)BEGIN if (reset=‘1’) then state <= S0; elsif (rising_edge(clk)) thencase state iswhen S0 => if (x=‘1’) then state <=S4;else state <=S1;end if; when S1 =>if (x=‘1’) then state <=S2;else state <=S1;end if; when S2 =>if (x=‘1’) then state <=S4;else state <=S3;end if; when S3 =>if (x=‘1’) then state <=S2;else state <=S6;end if; when S4 =>if (x=‘1’) then state <=S4;else state <=S5;end if; when S5 =>if (x=‘1’) then state <=S2;else state <=S6;end if; when S6 =>state <=S6; end case;end if;If (state = S3) then z <= ‘1’; else z<=‘0’;end if;end process;END behavior;Declare possible statesS0 [0]S1 [0]S2 [0]S3 [1]S4 [0]S5 [0]S6 [0]0+1Reset10 0001...010...10001...01...00...11...1011Output Z depends on state (Moore)State machine  One big case statement!Seattle Pacific University EE 1210 - Logic System Design MooreMealy-10VHDL Pattern Matcher - MealyLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY patternmatch ISPORT(clk: IN STD_LOGIC;reset: IN STD_LOGIC;x: IN STD_LOGIC;z: OUT STD_LOGIC);END patternmatch;ARCHITECTURE behavior OF patternmatch IS Type state_type is (S0,S1,S2,S4,S5,S6); SIGNAL state: state_type;BEGINPROCESS(reset,clk)BEGINif (reset=‘1’) then state <= S0; elsif (rising_edge(clk)) thencase state iswhen S0 => if (x=‘1’) then state <=S4;z<=‘0’;else state <=S1; z<=‘0’;end if;when S1 =>if (x=‘1’) then state <=S2;z<=‘0’;else state <=S1; z<=‘0’;end if;when S2 =>if (x=‘1’) then state <=S4;z<=‘0’;else state <=S5; z<=‘1’;end if;when S4 =>if (x=‘1’) then state <=S4;z<=‘0’;else state <=S5; z<=‘0’;end if;when S5 =>if (x=‘1’) then state <=S2;z<=‘0’;else state <=S6; z<=‘0’;end if;when S6 =>state <=S6; z<=‘0’;end case;end if;end process;END behavior;Declare possible statesOutput Z depends on state and input.S0 S1 S2 S4 S5 S6 (0+1)/0Reset/01/00/10/00/00/01/00/01/01/01/0No More S3!State machine  One big case statement!Seattle Pacific University EE 1210 -