Moore Machines Current State Next State State FlipFlops Combinational Logic For Next State Inputs Seattle Pacific University Clock Clock Comb Logic For Outputs Outputs A Moore FSM Outputs are a function of ONLY the current state Q Open Current State Output 0 0 5 0 10 0 15 1 EE 1210 Logic System Design Reset 0 N D N D N D 5 D N 10 N D N D 15 D open 1 N N D MooreMealy 1 Mealy Machines Current State Next State State FlipFlops Combinational Logic For Next State Inputs Seattle Pacific University Clock Clock Comb Logic For Outputs Outputs A Mealy FSM Outputs are a function of the current state and inputs WARNING Outputs are no longer synchronized with clock EE 1210 Logic System Design MooreMealy 2 Mealy FSM Diagrams In a Mealy FSM the outputs depend on the current state and the inputs We can t just label the states with the outputs anymore Reset 0 D 0 N D 0 N 0 N D 0 Outputs are associated with ARCS transitions between states Arc Labeling Input s Output s 5 D 1 N 0 N D 0 10 N D 1 15 D 0 N 0 Seattle Pacific University EE 1210 Logic System Design N D 0 MooreMealy 3 Mealy FSM Diagrams Efficiency Examine the 15 state But in Mealy FSMs we don t use states for outputs The 15 state is not needed We spend almost no time in it it s purpose was to output the signal OPEN Reset Reset 0 N D N D 0 N D N D 0 N 0 N D 0 N D 0 N 0 N D 0 5 5 5 D Reset D 1 N 0 10 N D 0 15 D open 1 N N 0 10 N D 0 N D Moore Seattle Pacific University 15 D 0 N 0 10 N D 1 N D 1 N D D 0 D 1 N N D 0 D 0 Efficient Mealy N D 0 Mealy EE 1210 Logic System Design MooreMealy 4 Mealy Gumball Machine Table Form Present Inputs State Reset 0 00 D 0 N D 0 N 0 N D 0 5 01 D 1 N 0 N D 0 10 10 N D 1 Efficient Mealy Assign numbers to states Seattle Pacific University Next State Output Q1 Q0 D N Q1 Q0 Open 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 X 0 1 0 X 1 0 0 X X X X X 0 1 0 X 1 0 0 X 0 0 0 X X X X X 0 0 0 X 0 0 1 X 0 1 1 X X X X X Notice that Output is now a function of state and inputs Only using three states State 11 is all don t cares EE 1210 Logic System Design MooreMealy 5 Mealy Gumball Machine Implementation D D D1 DN 00 Q1Q0 Q1 01 11 10 Q1Q0 01 11 10 00 0 0 x 1 00 0 1 x 0 01 0 1 x 0 01 1 0 x 0 11 x x x x 11 x x x x 10 1 0 x 0 10 0 1 x 1 N Open DN 00 Q1Q0 00 0 01 Q1 D0 DN 00 Q0 Q1 Q0 If we chose D FF s we don t have to convert Q s to FF inputs N D 01 11 10 0 x 0 0 0 x 1 11 x x x x 10 0 1 x 1 D1 DQ1 Q0 NQ0 D N Q1 D2 NQ0 D N Q0 DQ1 Q0 Open DQ0 NQ1 DQ1 Note that the output is a function of the state and the inputs N Seattle Pacific University EE 1210 Logic System Design MooreMealy 6 Pattern Matcher Moore and Mealy Machine that outputs 1 when last three inputs were 010 unless 100 has ever been seen Reset S0 0 0 1 0 0 1 S1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 0 S5 0 1 0 010 Moore S6 0 100 Seattle Pacific University S6 100 0 1 0 0 1 The purpose of state S3 is to output 1 can we get rid of it EE 1210 Logic System Design 10 0 0 0 1 S3 1 01 1 S4 S2 1 0 10 S5 0 1 0 0 0 S1 0 S2 1 01 S4 0 Reset 0 S0 Mealy MooreMealy 7 Pattern Matcher A Better Way If last three bits were 010 output 1 unless 100 has ever been seen Q2Q1Q0 are the last three bits shifted in in that order Q2 Q1 Q0 Shift Register En clk If last three bits were 100 enable is turned off and all shifting stops Q2 Q1 Q0 Q2 Q1 Q0 Shift in X Q2 Q1 Q0 Z Outputs Z 1 if sees 010 Seattle Pacific University EE 1210 Logic System Design MooreMealy 8 VHDL Pattern Matcher Moore BEGIN PROCESS reset clk BEGIN 1 1 0 0 if reset 1 then state S0 elsif rising edge clk then S4 S1 case state is 0 0 1 0 when S0 1 if x 1 then state S4 0 10 else state S1 1 S2 S5 State machine end if 1 0 01 0 when S1 One big case if x 1 then state S2 0 1 0 statement else state S1 100 S3 0 S6 end if 1 0 when S2 0 1 if x 1 then state S4 010 else state S3 end if LIBRARY ieee when S3 if x 1 then state S2 USE ieee std logic 1164 all else state S6 end if ENTITY patternmatch IS when S4 PORT if x 1 then state S4 clk IN STD LOGIC else state S5 end if reset IN STD LOGIC when S5 x IN STD LOGIC if x 1 then state S2 z OUT STD LOGIC else state S6 END patternmatch end if ARCHITECTURE behavior OF patternmatch IS when S6 Type state type is S0 S1 S2 S3 S4 S5 S6 state S6 SIGNAL state state type end case end if If state S3 then z 1 Declare possible states else z 0 Output Z depends on state Moore end if end process END behavior S0 0 Reset Seattle Pacific University EE 1210 Logic System Design MooreMealy 9 VHDL Pattern Matcher Mealy BEGIN PROCESS reset clk BEGIN 1 0 0 0 if reset 1 then state S0 S4 elsif rising edge clk then S1 case state is 1 0 0 0 when S0 1 0 if x 1 then state S4 z 0 0 0 else state S1 z 0 State machine S2 1 0 S5 end if 1 0 when S1 One big case 0 1 …