Voltage-controlled SwitchesMOS Semiconductor TransistorsSlide 3Voltage-controlled switchesAn nMOS InverterCMOS InverterCMOS NAND GateCMOS AND GateSeattle Pacific University EE 1210 - Logic System Design NMOS-CMOS-1Voltage-controlled Switches•In order to build circuits that implement logic, we need voltage-controlled switches•Control input = 1  Switch is closed•Control input = 0  Switch is openA BControl•This can be accomplished with electro-mechanical relays•Large, clunky, power-hungry•Transistors are a better way•Tiny, efficient, fastSourceDrainGateSeattle Pacific University EE 1210 - Logic System Design NMOS-CMOS-2Silicon Bulk (p-type)++++++++++ +++++++++++++e-e-e-e-e-e-e-e-e-+ ++++++ + +++++++++ +++++++++++++++++++++++++++++++MOS Semiconductor Transistorse-e-e-e-e-Sourcee-e-e-e-DrainGaten-type Sin-type SiSource WireDrain WireGate WireOxideP-type silicon: Excess positive charges (electron holes)N-type silicon: Excess negative charges (electrons)Oxide: InsulatorGate: Metal padIn this state, current (electrons) cannot flow between source and drain – switch is OPENSeattle Pacific University EE 1210 - Logic System Design NMOS-CMOS-3Silicon Bulk (p-type)++++++++++ ++++++++++++++ ++++++ + +++++++++ +++++++++++++++++++++++++++++++MOS Semiconductor Transistorse-e-e-e-e-Sourcee-e-e-e-DrainGaten-type Sin-type SiSource WireDrain WireGate WireOxidePlace a positive charge on the gate wire (gate = +5V)+5V+++ +++++The gate’s positive charge attracts negatively-charged electrons+e-e-e-e-e-e-e-e-e-This row of electrons forms a channel connecting the Source and Drain – Current can flow – Switch is CLOSEDe-e-Seattle Pacific University EE 1210 - Logic System Design NMOS-CMOS-4Voltage-controlled switchesLogic 1 on gate:Source and Drain connectedGateSourceDrainnMOS TransistorGateSourceDrainpMOS TransistorLogic 0 on gate:Source and Drain connectedGateSourceDrainGateSourceDrainnMOS: Good connector to GNDPoor connector to +5pMOS: Poor connector to GNDGood connector to +5Seattle Pacific University EE 1210 - Logic System Design NMOS-CMOS-5An nMOS Inverter•Issues•When transistor (switch) is closed, some current goes directly from 5V to GND•Wastes power; creates heat5VGND = 0VVinVout5VGND = 0VVinVoutReplace the switch with an NMOS transistor•When transistor (switch) is open, current must flow through the resistor•Wastes power; creates heatSeattle Pacific University EE 1210 - Logic System Design NMOS-CMOS-6CMOS InverterInput is 1Pull-up does not conductPull-down conductsOutput connected to GNDInput is 0Pull-up conductsPull-down does not conductOutput connected to Vdd5V = 1GND = 0Pull-up pMOStransistorPull-downnMOS transistorCurrentCurrentNote that there is never current leakage…GND+5VAZGND+5VAZGND+5VAZ10Seattle Pacific University EE 1210 - Logic System Design NMOS-CMOS-7CMOS NAND GateA = 1, B = 1Output is GND=0A = 0, B = 1 or A=1, B=0Output is Vdd=1Pull-uppMOS NetworkPull-downnMOS NetworkCurrentCurrent5V=1GND=0GND+5VABZ0111A = 0, B = 0 Output is Vdd=100CurrentGND+5VABZGND+5VABZGND+5VABZSeattle Pacific University EE 1210 - Logic System Design NMOS-CMOS-8CMOS AND GatePull-downpMOS NetworkPull-upnMOS NetworkBuild an AND gate by mirroring a NAND gate.Problem: nMOS is poor at transmitting 5V and pMOS is poor at transmitting GNDPull-uppMOS NetworkPull-downnMOS NetworkGND+5VABGND+5VZTake a NAND gate…and invert the outputTakes two more transistors, but works! This is the reason that NANDs/NORs are faster than