Voltage controlled Switches In order to build circuits that implement logic we need voltage controlled switches Control input 1 Switch is closed Control input 0 Switch is open A Source Control Gate B Drain This can be accomplished with electro mechanical relays Large clunky power hungry Transistors are a better way Tiny efficient fast Seattle Pacific University EE 1210 Logic System Design NMOS CMOS 1 MOS Semiconductor Transistors Source Wire Gate Wire Drain Wire e e n type Si Gate e e e e e Drain e Source e n type Si e e e Oxide e e e e Silicon Bulk p type e e P type silicon Excess positive charges electron holes N type silicon Excess negative charges electrons Oxide Insulator Gate Metal pad Seattle Pacific University In this state current electrons cannot flow between source and drain switch is OPEN EE 1210 Logic System Design NMOS CMOS 2 MOS Semiconductor Transistors Source Wire 5V Gate Wire Drain Wire n type Si Gate e e e e e e Drain e Source e e e n type Si Oxide e e e e e e Silicon Bulk p type e e e Place a positive charge on the gate wire gate 5V The gate s positive charge attracts negatively charged electrons This row of electrons forms a channel connecting the Source and Drain Current can flow Switch is CLOSED Seattle Pacific University EE 1210 Logic System Design NMOS CMOS 3 Voltage controlled switches Logic 1 on gate Source and Drain connected Gate Gate Drain Source nMOS Transistor nMOS Good connector to GND Poor connector to 5 Logic 0 on gate Source and Drain connected Gate Source Drain Source Gate Drain pMOS Transistor pMOS Poor connector to GND Good connector to 5 Seattle Pacific University Source EE 1210 Logic System Design Drain NMOS CMOS 4 An nMOS Inverter 5V Vin Vout 5V Replace the switch with an NMOS transistor Vout Vin GND 0V GND 0V Issues When transistor switch is closed some current goes directly from 5V to GND Wastes power creates heat When transistor switch is open current must flow through the resistor Wastes power creates heat Seattle Pacific University EE 1210 Logic System Design NMOS CMOS 5 CMOS Inverter 5V 5V Pull up pMOS transistor Current Z Z A Pull down nMOS transistor Z GND 0 A1 GND 5V 5V 1 A0 Current GND Input is 1 Pull up does not conduct Pull down conducts Output connected to GND GND Input is 0 Pull up conducts Pull down does not conduct Output connected to Vdd Note that there is never current leakage Seattle Pacific University EE 1210 Logic System Design NMOS CMOS 6 CMOS NAND Gate 5V Pull up pMOS Network Current A 0 B 1 or A 1 B 0 Output is Vdd 1 5V Z Z A A0 Pull down nMOS Network B GND 5V 1 B1 5V GND 5V Current Z GND 0 A1 Z A0 Current B1 GND Seattle Pacific University A 1 B 1 Output is GND 0 B 0 A 0 B 0 Output is Vdd 1 EE 1210 Logic System Design GND NMOS CMOS 7 CMOS AND Gate 5V 5V A 5V Pull up nMOS Network B Z Pull down pMOS Network GND Build an AND gate by mirroring a NAND gate Problem nMOS is poor at transmitting 5V and pMOS is poor at transmitting GND Seattle Pacific University Z Pull up pMOS Network A Pull down nMOS Network B GND GND Take a NAND gate and invert the output Takes two more transistors but works This is the reason that NANDs NORs are faster than ANDs ORs EE 1210 Logic System Design NMOS CMOS 8