Objective Pipelining Design Processor for Alpha Subset Interesting but not overwhelming quantity High level functional blocks September 18 2002 Topics 1 Initial Design Topics 2 Objective Instruction formats Instruction processing Principles of pipelining Inserting pipe registers One instruction at a time Single cycle per instruction Follows H P Ch A 1 Data Hazards Stalling and Forwarding Systematic testing of hazard handling logic Control Hazards Stalling Predict not taken Exceptions Multicycle Instructions Refined Design 5 stage pipeline Similar to early RISC processors Follows H P Ch A 2 3 Goal approach 1 cycle per instruction but with shorter cycle time What Makes it Hard Hazards exceptions A 4 6 2 Page 1 CS 740 F 02 Alpha Arithmetic Instructions Alpha Load Store Instructions RR type instructions addq subq xor bis cmplt rc ra funct rb Op ra 31 26 25 21 rb 000 0 funct rc 20 16 15 13 12 11 5 4 0 Load Ra Mem Rb offset Store Mem Rb offset Ra RI type instructions addq subq xor bis cmplt rc ra funct ib Op ra ib 1 funct rc 31 26 25 21 20 13 12 11 5 4 0 Encoding ib is 8 bit unsigned literal Operation Op field 0x10 0x10 0x11 0x11 0x11 0x20 0x29 0x20 0x40 0x24 cmplt 0x11 0x4D 3 ra 25 21 rb 20 16 offset 15 0 Encoding offset is 16 bit signed offset Operation Op field ldq stq funct field addq subq bis xor cmoveq Op 31 26 CS 740 F 02 4 Page 2 0x29 0x2D CS 740 F 02 Branch Instructions Transfers of Control jmp jsr ret Ra PC 4 PC Rb Cond Branch PC Cond Ra PC 4 disp 4 PC 4 Op ra disp 31 26 25 21 20 0 Encoding disp is 21 bit signed displacement Operation Op field Cond beq bne 0x39 0x3D ra disp 25 21 20 0 Operation br bsr 5 25 21 jmp jsr ret Branch Subroutine br bsr Ra PC 4 PC PC 4 disp 4 Op ra 31 26 rb Hint 20 16 15 0 Encoding High order 2 bits of Hint encode jump type Remaining bits give information about predicted destination Hint does not affect functionality Jump Type Hint 15 14 Ra 0 Ra 0 31 26 0x1A 00 01 10 call pal Op field 0x30 0x34 0x00 Number 31 26 25 0 Use as halt instruction CS 740 F 02 6 Page 3 CS 740 F 02 Instruction Encoding 0x0 40220403 addq r1 r2 r3 0x4 4487f805 xor r4 0x3f r5 0x8 a4c70abc ldq r6 2748 r7 0xc b5090123 stq r8 291 r9 0x10 e47ffffb beq r3 0 0x14 d35ffffa bsr r26 0 r31 0x18 6bfa8001 ret r31 r26 1 0x1c 000abcde call pal Decoding Examples 0x0 40220403 0x8 a4c70abc 4 0 2 2 0 4 0 3 0100 0000 0010 0010 0000 0100 0000 0011 10 01 02 0x10 e47ffffb beq 20 03 r3 0 e 4 7 f f f f b 1110 0100 0111 1111 1111 1111 1111 1011 0xabcde Object Code 39 Instructions encoded in 32 bit words Program behavior determined by bit encodings Disassembler simply converts these words to readable instructions 7 addq r1 r2 r3 03 Target CS 740 F 02 8 Page 4 1ffffb 510 ldq r6 2748 r7 a 4 c 7 0 a b c 1010 0100 1100 0111 0000 1010 1011 1100 29 06 07 0x18 6bfa8001 0abc 274810 ret r31 r26 1 6 b f a 8 0 0 1 0110 1011 1111 1010 1000 0000 0000 0001 1a 1f 1a 2 3110 2610 16 Current PC 4 Increment 4 5 Disp 0 CS 740 F 02 Datapath IF instruction fetch ID instruction decode register fetch Hardware Units EX execute address calculation MEM memory access WB Storage write back Instruction Memory Fetch 32 bit instructions Data Memory Load store 64 bit data Register Array Storage for 32 integer registers Two read ports can read two registers at once Single write port Zero Test Instr 15 0 20 0 P C datIn Xtnd 2 25 21 regA 20 16 regB Instr Mem datW 20 13 4 0 Data Mem Xtnd regW datOut datA Reg Array datB addr aluA ALU aluB Functional Units Wdest 25 21 4 IncrPC Wdata 9 CS 740 F 02 4 Xtnd ALU Zero Test 10 Page 5 PC incrementer Sign extender Arithmetic and logical instructions Detect whether operand 0 CS 740 F 02 RR type instructions Active Datapath for RR RI RR type instructions addq subq xor bis cmplt rc ra funct rb Op ra 31 26 25 21 rb 000 0 funct rc 20 16 15 13 12 11 5 4 0 Instr datIn Data Mem 25 21 IF Instruction fetch 20 16 P C IR IMemory PC PC PC 4 Instr Mem regB datW 20 13 ID Instruction decode register fetch regA regW datOut datA Reg Array datB 4 Wdest IncrPC Ex Execute Wdata ALUOutput A op B ALU Operation MEM Memory Input B selected according to instruction type datB for RR IR 20 13 for RI ALU function set according to operation type nop WB Write back Register IR 4 0 ALUOutput 11 ALU aluB 4 0 A Register IR 25 21 B Register IR 20 16 addr aluA CS 740 F 02 12 Page 6 Write Back To Rc CS 740 F 02 Active Datapath for RR RI Instr RI type instructions RI type instructions addq subq xor bis cmplt rc ra funct ib datIn Data Mem 25 21 IF Instruction fetch IR IMemory PC PC PC 4 ID 20 16 P C Instr Mem datA Reg Array regW addr aluA ALU nop WB Write back Register IR 4 0 ALUOutput ALU Operation funct rc 11 5 4 0 Ex Execute Input B selected according to instruction type datB for RR IR 20 13 for RI ALU function set according to operation type ALUOutput A op B MEM Memory nop WB Write back Write Back 13 1 12 A Register IR 25 21 B IR 20 13 ALUOutput A op B MEM Memory ib 20 13 ID Instruction decode register fetch Wdata Ex Execute ra 25 21 IR IMemory PC PC PC 4 Wdest IncrPC A Register IR 25 21 B Register IR 20 16 Op 31 26 IF Instruction fetch aluB datB 4 0 4 regB datW 20 13 datOut regA To Rc Register IR 4 0 ALUOutput CS 740 F 02 14 Page 7 CS 740 F 02 Load instruction Active Datapath for Load Store Load Ra Mem Rb offset Instr Op ra 31 26 25 21 rb 20 16 15 0 offset 15 0 IF Instruction fetch P C IR IMemory PC PC PC 4 datIn 25 21 regA 20 16 regB Instr Mem datW regW ID Instruction decode register fetch datA Reg Array datB Store aluA datOut addr ALU aluB Load Wdest B Register IR 20 16 25 21 Ex Execute 4 IncrPC ALUOutput B SignExtend IR 15 0 MEM Memory ALU Operation Used to compute address A input set to extended IR 15 0 ALU function set to add Mem Data DMemory ALUOutput WB Write back Register IR 25 21 Mem Data 15 Data …
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