Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture David I August Daniel A Connors Scott A Mahlkey John W Sias Kevin M Crozier Ben Chung Cheng Patrick R Eaton Qudus B Olaniran Wen mei W Hwu Center for Reliable and High Performance Computing University of Illinois Urbana Champaign IL 61801 faugust dconnors sias crozier bccheng eaton mrq hwug crhc uiuc edu Abstract Explicitly Parallel Instruction Computing EPIC architectures require the compiler to express program instruction level parallelism directly to the hardware EPIC techniques which enable the compiler to represent control speculation data dependence speculation and predication have individually been shown to be very effective However these techniques have not been studied in combination with each other This paper presents the IMPACT EPIC Architecture to address the issues involved in designing processors based on these EPIC concepts In particular we focus on new execution and recovery models in which microarchitectural support for predicated execution is also used to enable efficient recovery from exceptions caused by speculatively executed instructions This paper demonstrates that a coherent framework to integrate the three techniques can be elegantly designed to achieve much better performance than each individual technique could alone provide 1 Introduction The performance of modern processors is increasingly dependent on their ability to execute multiple instructions per cycle While mainstream microprocessors in 1990 executed at most one instruction per cycle 5 7 those in 1995 had the ability to execute up to four instructions per cycle 6 By the year 2000 hardware technology will be capable of producing microprocessors that execute up to sixteen instructions per clock cycle Such rapid dramatic increases in hardware parallelism have placed tremendous pressure on compiler technology Without appropriate instruction set architecture support it can be very costly in terms of code size and compile time for the compiler to expose sufficient amounts of Instruction Level Parallelism ILP to the hardware As a result an increasingly important aspect of computer architecture is to provide the compiler with means to control compile time and run time costs while enhancing the amount of ILP visible to the hardware The term Explicitly Parallel Instruction Computing EPIC was coined recently by Hewlett Packard and Intel in their joint announcement of the IA 64 instruction set 10 It refers to archi y Hewlett Packard Laboratories Hewlett Packard Palo Alto CA 94304 mahlke hpl hp com tectures in which features are provided to facilitate compiler enhancements of ILP in all programs It is natural to expect that the coming generation of EPIC architectures will have features to overcome the worst impediments to a compiler s ability to enhance ILP frequent control transfers and ambiguous memory dependences Three such features have been proposed and studied in the literature Predication allows the compiler to overlap the execution of independent control constructs without code explosion 12 It also enables the compiler to reduce the frequency of branch instructions to reduce branch mispredictions and to perform sophisticated control flow optimizations 16 19 23 Predication does this at the cost of increased fetch utilization Control speculation allows the compiler to judiciously eliminate control dependences at the cost of increased register consumption and instruction overhead 14 21 Data dependence speculation enables the compiler to overcome ambiguous memory dependences also at the cost of increased register consumption and instruction overhead 8 12 Although these three techniques have been studied individually issues involved in synthesizing a coherent architecture that supports all of them have not been addressed in the literature In 16 the benefit of predication support was studied with a predication compiler However the accompanying control speculation model based on silent instructions did not precisely detect all exceptions Sentinel speculation was introduced in 14 to provide accurate detection of and recovery from exceptions however the sentinel speculation model was not developed in the context of a predicated architecture 8 presented a compiler directed data dependence speculation model based on the Memory Conflict Buffer MCB However the model was not defined in the context of a predicated architecture Furthermore it used silent instructions to eliminate spurious exceptions caused by data speculative memory loads and their dependent instructions preventing accurate detection of and recovery from all exceptions The primary contribution of this paper is the new IMPACT EPIC Architecture framework that elegantly supports all three features A machine based on the IMPACT EPIC Architecture framework will allow the compiler to achieve several key improvements surpassing the current state of the art First the compiler can speculate both control and data flow in predicated code without introducing spurious exceptions data page faults Translation Look aside Buffer TLB misses or long latency cache misses Second the microarchitectural support required by predicated instructions can also be used to support inline recovery for both control and data speculation Third a single recovery model can be used for both control and data speculation simplifying the compiler code generation scheme The secondary contribution of this paper is to present some preliminary experimental results based on a prototype compiler for the IMPACT EPIC Architecture and initial insights into the performance characteristics of the architecture These results will show that combining control speculation data dependence speculation and predicated execution into a coherent architecture provides a significantly greater performance potential than any one of these techniques alone could provide and that an efficient mechanism can be designed for detection of and recovery from speculative exceptions in such an architecture 2 Background and motivation The three enabling features of the IMPACT EPIC Architecture control speculation data dependence speculation and predicated execution are examined in this section First the individual merits of each feature are presented Then the potential benefits of combining the features into a coherent architecture are described A running example consisting of the if then else C statement shown in Figure 1a is used to focus the
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