CS 740 Computer Architecture Fall 2003 Assignment 2 Handling Pipeline Hazards Assigned Wednesday Sept 17 Due Monday Sept 29 1 Policy You should work in groups of 3 people in solving the problems for this assignment A group of 2 will only be allowed if the class size does not divide evenly by 3 groups of 1 are definitely not permitted You should turn in a single report for your entire group identifying all of the group members 2 Logistics Any clarifications and revisions to the assignment will be posted on the class bboard and Web page For this assignment you will want to retrieve the file afs cs cmu edu academic class 15740 f03 public asst asst2 files tar You will hand in a hard copy formatted text document for this assignment You should also provide us with a version of your code file stages c Do this by naming your file last stages c where last is the last name of one of your group members and copying this file to the directory afs cs cmu edu academic class 15740 f03 public asst asst2 handin Include as comments near the beginning of this file the identities of all members of your group 3 Introduction The purpose of this assignment is to gain a deeper understanding of how pipelined processors are implemented Our method of doing this will be to create a C program that simulates pAlpha a pipelined implementation of a subset of the Alpha architecture Although C is not an ideal language for describing and simulating hardware designs one can get a high level view of how the hardware operates by using an appropriate coding style You can pick up the entire set of files by copying and untarring the file files tar The source files include the following alpha h Macros defining the pAlpha instruction format These are generally consistent with the Alpha architecture sim h sim c Simulator framework 1 stages h stages c A partial implementation of the pipeline stages You will need to fix and extend the code in the file stages c In addition there are some files containing utility routines for the simulator user interface code plus a subdirectory called demos containing some sample machine programs The code can be compiled to generate two different user interfaces alpha tty A batch oriented interface that prints all kinds of trace information out as it executes alpha tk A graphic user interface based on Tcl Tk that lets you watch and control the simulator execution The GUI version is far more pleasant to use The batch interface is provided as the fall back on systems that do not support Tcl Tk Also the batch version works better for doing systematic testing of your solution You may want modify the file alpha tk to include pathnames for the directory in which you install your code A correctly working version of the simulator that runs on the class alphas has been installed as afs cs cmu edu academic class 15740 f03 public sim solve tk You might find it useful as an aid in debugging your own code 4 pAlpha Instruction Set Refer to page 45 of the lecture 2 notes for a description of the Alpha instruction formats The pAlpha instruction set includes only 7 classes of instructions Arithmetic Operations These are ADDQ SUBQ ADDL SUBL CMPULT CMPLT BIS ORNOT XOR CMOVEQ and CMOVNE These instructions can be of either register register or register immediate format Load The LDQ instruction Store The STQ instruction Conditional Branches These are BEQ and BNE Unconditional Branches These are BR and BSR Jump The JMP instruction Call PAL This instruction is used to halt the simulator The intention of the implementation is to use the semantics of the Alpha instruction set This includes requiring memory references to be aligned etc When you complete this lab assignment all instructions will be fully implemented 2 3 Figure 1 Detailed pAlpha Pipeline Organization From class handouts Mem In Adata IF ID ID EX EX In Adata EX MEM Zero Test Instr 15 0 Xtnd 20 0 P C Instr Mem 25 21 regA 20 16 regB 20 13 regW 4 0 IncrPC Data Mem Xtnd 2 20 16 4 datIn Adata datW 25 21 Branch Flag MEM WB datOut datA addr aluA Reg Array ALU ALUout aluB datB B Src W Dst W Wdest Dst A Src A Src W Dst Wdata EX In Bdata Branch Flag Target PC ID EX IF ID IF ID Instr Mem Reg File EX MEM EX MEM WB MEM Data Mem Next PC Write Back Reg Data Figure 2 Simplified pAlpha Pipeline Organization 5 pAlpha Implementation Figure 1 illustrates the structure of the pAlpha implementation This implementation is styled after the MIPS pipeline described in Appendix A of the textbook The figure is taken from the class handouts The rectangular blocks in the figure denote pipe registers a set of registers that hold the state used by the pipeline stages Note that the program counter PC is one such pipe register while the others are labeled by the states between which they sit Embedded within the stages are additional state elements the instruction memory in IF the register file in ID and the data memory in MEM To keep things simple the instruction data memories are distinct In the actual processor there are indeed separate instruction and data caches but these both access a common main memory Also shown are the major functional units an adder in IF to increment the program counter and an ALU in EX to compute data values effective addresses and branch targets and a Zero Test block in EX to compute branch conditions Also shown are the bypass paths used to support register forwarding Figure 2 shows a simplified version of the pipeline structure The rounded rectangles denote the logic of each of the pipeline stages while the arcs denote the signal connections A pipe register has a current state and a next state Each pipeline stage takes the current state of one or more pipe registers and generates the next state of one or more pipe registers One cycle of the pipeline consists of two phases during the operate phase the pipe stages compute new values for the registers while during the update phase the pipe registers store these values and deliver them as inputs to the next stage Note that there is no explicit write back stage WB Instead the write back logic is incorporated into the decode stage ID to avoid a conflict at the register file The version of the pipeline provided to you has serious deficiencies In particular stalling and forwarding are not used to handle hazards Therefore both data and control hazards are handled incorrectly Furthermore none of the conditional move instructions are fully implemented Otherwise the design should be correct Please notify us if you find
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