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CMU CS 15740 - assignment

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CS 740, Computer Architecture, Fall 2003Assignment 2:Handling Pipeline HazardsAssigned: Wednesday, Sept. 17Due: Monday, Sept. 291 PolicyYou should work in groups of 3 people in solving the problems for this assignment. (A group of 2 will onlybe allowed if the class size does not divide evenly by 3—groups of 1 are definitely not permitted.) Youshould turn in a single report for your entire group, identifying all of the group members.2 LogisticsAny clarifications and revisions to the assignment will be posted on the class bboard and Web page.For this assignment, you will want to retrieve the file:/afs/cs.cmu.edu/academic/class/15740-f03/public/asst/asst2/files.tarYou will hand in a hard copy—formatted text—document for this assignment.You should also provide us with a version of your code file stages.c. Do this by naming your filelast-stages.c, where last is the last name of one of your group members, and copying this file to thedirectory/afs/cs.cmu.edu/academic/class/15740-f03/public/asst/asst2/handinInclude as comments near the beginning of this file the identities of all members of your group.3 IntroductionThe purpose of this assignment is to gain a deeper understanding of how pipelined processors are imple-mented. Our method of doing this will be to create a C program that “simulates” pAlpha, a pipelinedimplementation of a subset of the Alpha architecture. Although C is not an ideal language for describingand simulating hardware designs, one can get a high level view of how the hardware operates by using anappropriate coding style.You can pick up the entire set of files by copying and untarring the file files.tar. The source filesinclude the following:alpha.h : Macros defining the pAlpha instruction format. These are generally consistent with the Alphaarchitecture.sim.h, sim.c Simulator framework.1stages.h, stages.c A partial implementation of the pipeline stages. You will need to fix and extendthe code in the file stages.c.In addition, there are some files containing utility routines for the simulator, user interface code, plus asubdirectory called demos containing some sample machine programs.The code can be compiled to generate two different user interfaces:alpha tty A batch-oriented interface that prints all kinds of trace information out as it executes.alpha tk A graphic-user interface based on Tcl/Tk that lets you watch and control the simulator execution.The GUI version is far more pleasant to use. The batch interface is provided as the fall-back on systems thatdo not support Tcl/Tk. Also, the batch version works better for doing systematic testing of your solution.You may want modify the file alpha tk to include pathnames for the directory in which you install yourcode.A correctly working version of the simulator that runs on the class alphas has been installed as:/afs/cs.cmu.edu/academic/class/15740-f03/public/sim/solve_tkYou might find it useful as an aid in debugging your own code.4 pAlpha Instruction SetRefer to page 45 of the lecture 2 notes for a description of the Alpha instruction formats.The pAlpha instruction set includes only 7 classes of instructions:Arithmetic Operations These are ADDQ, SUBQ, ADDL, SUBL, CMPULT, CMPLT, BIS, ORNOT, XOR,CMOVEQ, and CMOVNE. These instructions can be of either register-register or register-immediateformat.Load The LDQ instruction.Store The STQ instruction.Conditional Branches These are BEQ and BNE.Unconditional Branches These are BR and BSR.Jump The JMP instruction.Call PAL This instruction is used to halt the simulator.The intention of the implementation is to use the semantics of the Alpha instruction set. This includesrequiring memory references to be aligned, etc. When you complete this lab assignment, all instructionswill be fully implemented.2PCInstr.Mem.Reg.ArrayregAregBregWdatWdatAdatBALU25:2120:16+4DataMem.datInaddrdatOutaluAaluBIncrPCInstr4:0WdestWdata20:13Xtnd25:21WdataWdest15:0Xtnd << 2ZeroTest25:21WdataWdest20:0Branch Flag25:21WdataWdestIF/ID ID/EX EX/MEM MEM/WBAdataALUoutWDstASrcBSrcWDstASrcWDst25:2120:16Mem In AdataEX In AdataEX In BdataFigure 1: Detailed pAlpha Pipeline Organization (From class handouts)3PC IF/IDInstr.Mem.Reg.FileDataMem.ID/EX EX/MEM MEM/WBIF ID EX MEMWrite Back Reg. & DataNext PCBranch Flag & TargetFigure 2: Simplified pAlpha Pipeline Organization5 pAlpha ImplementationFigure 1 illustrates the structure of the pAlpha implementation. This implementation is styled after theMIPS pipeline described in Appendix A of the textbook. The figure is taken from the class handouts. Therectangular blocks in the figure denote pipe registers, a set of registers that hold the state used by the pipelinestages. Note that the program counter PC is one such pipe register, while the others are labeled by thestates between which they sit. Embedded within the stages are additional state elements: the instructionmemory in IF, the register file in ID, and the data memory in MEM. To keep things simple, the instructiondata memories are distinct. In the actual processor, there are indeed separate instruction and data caches,but these both access a common main memory. Also shown are the major functional units: an adder in IF toincrement the program counter, and an ALU in EX to compute data values, effective addresses, and branchtargets, and a “Zero Test” block in EX to compute branch conditions. Also shown are the bypass paths usedto support register forwarding.Figure 2 shows a simplified version of the pipeline structure. The rounded rectangles denote the logic ofeach of the pipeline stages, while the arcs denote the signal connections.A pipe register has a current state and a next state. Each pipeline stage takes the current state of one or morepipe registers and generates the next state of one or more pipe registers. One cycle of the pipeline consistsof two phases: during the operate phase the pipe stages compute new values for the registers, while duringthe update phase, the pipe registers store these values and deliver them as inputs to the next stage.Note that there is no explicit write-back stage WB. Instead, the write-back logic is incorporated into thedecode stage ID, to avoid a conflict at the register file.The version of the pipeline provided to you has serious deficiencies. In particular, stalling and forwarding arenot used to handle hazards. Therefore both data and control hazards are handled incorrectly. Furthermore,none of the conditional move instructions are fully implemented. Otherwise, the


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