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CMU CS 15740 - Temperature-Aware Microarchitecture

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Temperature-Aware Microarchitecture†Kevin Skadron,‡Mircea R. Stan,‡Wei Huang,†Sivakumar Velusamy,†Karthik Sankaranarayanan, and†David Tarjan∗†Dept. of Computer Science, ‡Dept. of Electrical and Computer EngineeringUniversity of Virginia, Charlottesville, VA{skadron,siva,karthick,dtarjan}@cs.virginia.edu, {mircea,wh6p}@virginia.eduAbstractWith power density and hence cooling costs rising exponen-tially, processor packaging can no longer be designed for the worstcase, and there is an urgent need for runtime processor-level tech-niques that can regulate operating temperature when the pack-age’s capacity is exceeded. Evaluating such techniques, however,requires a thermal model that is practical for architectural studies.This paper describes HotSpot, an accurate yet fast model basedon an equivalent circuit of thermal resistances and capacitancesthat correspond to microarchitecture blocks and essential aspectsof the thermal package. Validation was performed using finite-element simulation. The paper also introduces several effectivemethods for dynamic thermal management (DTM): “temperature-tracking” frequency scaling, localized toggling, and migratingcomputation to spare hardware units. Modeling temperature atthe microarchitecture level also shows that power metrics are poorpredictors of temperature, and that sensor imprecision has a sub-stantial impact on the performance of DTM.1. IntroductionIn recent years, power density in microprocessors has dou-bled every three years [3, 17], and this rate is expected to in-crease within one to two generations as feature sizes and frequen-cies scale faster than operating voltages [25]. Because energyconsumed by the microprocessor is converted into heat, the cor-responding exponential rise in heat density is creating vast dif-ficulties in reliability and manufacturing costs. At any power-dissipation level, heat being generated must be removed from thesurface of the microprocessor die, and for all but the lowest-powerdesigns today, these cooling solutions have become expensive. Forhigh-performance processors, cooling solutions are rising at $1–3or more per watt of heat dissipated [3, 12], meaning that coolingcosts are rising exponentially and threaten the computer industry’sability to deploy new systems.Power-aware design alone has failed to stem this tide, requir-ing temperature-aware design at all system levels, including theprocessor architecture. Temperature-aware design will make useof power-management techniques, but probably in ways that aredifferent from those used to improve battery life or regulate peak∗This work was conducted while David Tarjan visited U.Va. during hisdiploma program at the Swiss Federal Institute of Technology Z¨urich.power. Localized heating occurs much faster than chip-wide heat-ing; since power dissipation is spatially non-uniform across thechip, this leads to “hot spots” and spatial gradients that can causetiming errors or even physical damage. These effects evolve overtime scales of hundreds of microseconds or milliseconds. Thismeans that power-management techniques, in order to be used forthermal management, must directly target the spatial and temporalbehavior of operating temperature. In fact, many low-power tech-niques have little or no effect on operating temperature, becausethey do not reduce power density in hot spots, or because they onlyreclaim slack and do not reduce power and temperature when noslack is present. Temperature-aware design is therefore a distinctalbeit related area of study.Temperature-specific design techniques to date have mostly fo-cused on the thermal package (heat sink, fan, etc.). If the pack-age is designed for worst-case power dissipation, they must bedesigned for the most severe hot spot that could arise, which isprohibitively expensive. Yet these worst-case scenarios are rare:the majority of applications, especially for the desktop, do not in-duce sufficient power dissipation to produce the worst-case tem-peratures. A package designed for the worst case is excessive.To reduce packaging cost without unnecessarily limiting per-formance, it has been suggested [4, 12, 13] that the packageshould be designed for the worst typical application. Any applica-tions that dissipate more heat than this cheaper package can man-age should engage an alternative, runtime thermal-managementtechnique (dynamic thermal management or DTM). Since typi-cal high-power applications still operate 20% or more below theworst case [12], this can lead to dramatic savings. This is the phi-losophy behind the thermal design of the Intel Pentium 4 [12]. Ituses a thermal package designed for a typical high-power applica-tion, reducing the package’s cooling requirement by 20% and itscost accordingly. Should operating temperature ever exceed a safetemperature, the clock is stopped (we refer to this as global clockgating) until the temperature returns to a safe zone. This protectsagainst both timing errors and physical damage that might resultfrom sustained high-power operation, from operation at higher-than-expected ambient temperatures, or from some failure in thepackage. As long as the threshold temperature that stops the clock(the trigger threshold) is based on the hottest temperature in thesystem, this approach successfully regulates temperature.The Need for Architecture-Level Thermal Management.These chip-level hardware techniques illustrate both the benefitsand challenges of runtime thermal management: while it can sub-stantially reduce cooling costs and still allow typical applicationsto run at peak performance, these techniques also reduce perfor-mance for any applications that exceed the thermal design point.Such performance losses can be substantial with chip-wide tech-niques like global clock gating, with a 27% slowdown for ourhottest application, art.Instead of using chip-level thermal-management techniques,we argue that the microarchitecture has an essential role to play.The microarchitecture is unique in its ability to use runtime knowl-edge of application behavior and the current thermal status ofdifferent units of the chip to adjust execution and distribute theworkload in order to control thermal behavior. In this paper,we show that architecture-level thermal modeling exposes archi-tectural techniques that regulate temperature with lower perfor-mance cost than chip-wide techniques by exploiting instruction-level parallelism (ILP). For example, one of the best


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CMU CS 15740 - Temperature-Aware Microarchitecture

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