Objective Basic Pipelining Design Processor for Alpha Subset Interesting but not overwhelming quantity High level functional blocks October 25 2007 Initial Design One instruction at a time Single cycle per instruction Topics Refined Design Objective Instruction formats Instruction processing Principles of pipelining Inserting pipe registers 5 stage pipeline Similar to early RISC processors Goal approach 1 cycle per instruction but with shorter cycle time 2 Alpha Arithmetic Instructions Alpha Load Store Instructions RR type instructions addq subq xor bis cmplt rc ra funct rb Op ra rb 000 0 funct rc 31 26 25 21 20 16 15 13 12 11 5 Load Ra Mem Rb offset Store Mem Rb offset Ra 4 0 RI type instructions addq subq xor bis cmplt rc ra funct ib Op ra ib 1 funct rc 31 26 25 21 20 13 12 11 5 4 0 Encoding ib is 8 bit unsigned literal Operation Op field 0x10 0x10 0x11 0x11 0x11 0x20 0x29 0x20 0x40 0x24 cmplt 0x11 0x4D 3 Op ra 31 26 25 21 rb 20 16 offset 15 0 Encoding offset is 16 bit signed offset Operation Op field ldq stq funct field addq subq bis xor cmoveq CS 740 F 07 CS 740 F 07 4 Page 1 0x29 0x2D CS 740 F 07 Branch Instructions Transfers of Control jmp jsr ret Ra PC 4 PC Rb Cond Branch PC Cond Ra PC 4 disp 4 PC 4 Op ra disp 31 26 25 21 20 0 Encoding disp is 21 bit signed displacement Operation Op field Cond beq bne 0x39 0x3D ra disp 25 21 20 0 Operation 15 0 0x00 Number 31 26 25 0 Use as halt instruction 5 CS 740 F 07 6 CS 740 F 07 Instruction Encoding 0x0 40220403 addq r1 r2 r3 0x4 4487f805 xor r4 0x3f r5 0x8 a4c70abc ldq r6 2748 r7 0xc b5090123 stq r8 291 r9 0x10 e47ffffb beq r3 0 0x14 d35ffffa bsr r26 0 r31 0x18 6bfa8001 ret r31 r26 1 call pal Decoding Examples 0x0 40220403 addq r1 r2 r3 0x8 a4c70abc 4 0 2 2 0 4 0 3 0100 0000 0010 0010 0000 0100 0000 0011 10 01 02 0x10 e47ffffb beq 20 03 r3 0 e 4 7 f f f f b 1110 0100 0111 1111 1111 1111 1111 1011 0xabcde Object Code 39 Instructions encoded in 32 bit words Program behavior determined by bit encodings Disassembler simply converts these words to readable instructions 7 Hint call pal 0x30 0x34 0x1c 000abcde rb 20 16 00 01 10 Op field br bsr 25 21 jmp jsr ret Branch Subroutine br bsr Ra PC 4 PC PC 4 disp 4 Op ra 31 26 Encoding High order 2 bits of Hint encode jump type Remaining bits give information about predicted destination Hint does not affect functionality Jump Type Hint 15 14 Ra 0 Ra 0 31 26 0x1A 03 Target CS 740 F 07 8 Page 2 1ffffb 510 ldq r6 2748 r7 a 4 c 7 0 a b c 1010 0100 1100 0111 0000 1010 1011 1100 29 06 07 0x18 6bfa8001 0abc 274810 ret r31 r26 1 6 b f a 8 0 0 1 0110 1011 1111 1010 1000 0000 0000 0001 1a 1f 1a 2 3110 2610 16 Current PC 4 Increment 4 5 Disp 0 CS 740 F 07 Datapath IF ID instruction fetch instruction decode register fetch Hardware Units EX MEM execute address calculation memory access WB Storage write back Instruction Memory Fetch 32 bit instructions Data Memory Load store 64 bit data Register Array Storage for 32 integer registers Two read ports can read two registers at once Single write port Zero Test Instr 15 0 20 0 P C datIn Data Mem Xtnd Xtnd 2 25 21 regA 20 16 regB Instr Mem datW 20 13 datOut datA Reg Array regW datB addr aluA ALU aluB Functional Units 4 0 Wdest 25 21 4 IncrPC Wdata 9 4 Xtnd ALU Zero Test CS 740 F 07 10 RR type instructions 25 21 20 16 15 13 12 11 5 CS 740 F 07 Active Datapath for RR RI RR type instructions addq subq xor bis cmplt rc ra funct rb Op ra rb 000 0 funct rc 31 26 PC incrementer Sign extender Arithmetic and logical instructions Detect whether operand 0 Instr datIn Data Mem 4 0 IF Instruction fetch P C IR IMemory PC PC PC 4 25 21 regA 20 16 regB Instr Mem datW 20 13 ID Instruction decode register fetch regW datOut datA Reg Array datB 4 Wdest IncrPC Ex Execute Wdata ALUOutput A op B ALU Operation MEM Memory Input B selected according to instruction type datB for RR IR 20 13 for RI ALU function set according to operation type nop WB Write back Register IR 4 0 ALUOutput 11 ALU aluB 4 0 A Register IR 25 21 B Register IR 20 16 addr aluA CS 740 F 07 12 Page 3 Write Back To Rc CS 740 F 07 RI type instructions Load instruction RI type instructions addq subq xor bis cmplt rc ra funct ib Op ra ib 1 funct rc 31 26 25 21 20 13 12 11 5 Load Ra Mem Rb offset 4 0 IF Instruction fetch B Register IR 20 16 ALUOutput B SignExtend IR 15 0 ALUOutput A op B MEM Memory MEM Memory Mem Data DMemory ALUOutput nop WB Write back WB Write back Register IR 25 21 Mem Data Register IR 4 0 ALUOutput 13 CS 740 F 07 14 Instr Store Mem Rb offset Ra datIn 25 21 regA 20 16 regB datW regW datA Reg Array datB Store aluA datOut rb 20 16 offset 15 0 IR IMemory PC PC PC 4 ALU aluB Load ID Instruction decode register fetch Wdest A Register IR 25 21 B Register IR 20 16 IncrPC Used to compute address A input set to extended IR 15 0 ALU function set to add ra 25 21 IF Instruction fetch addr 25 21 ALU Operation Op 31 26 Data Mem Xtnd CS 740 F 07 Store instruction Active Datapath for Load Store 15 15 0 Ex Execute Ex Execute 4 offset ID Instruction decode register fetch A Register IR 25 21 B IR 20 13 Instr Mem rb 20 16 IR IMemory PC PC PC 4 ID Instruction decode register fetch P C ra 25 21 IF Instruction fetch IR IMemory PC PC PC 4 15 0 Op 31 26 Ex Execute Wdata ALUOutput B SignExtend IR 15 0 Memory Operation MEM Memory Read for load write for store Write Back DMemory ALUOutput A To Ra for load None for store WB Write back nop CS 740 F 07 16 Page 4 CS 740 F 07 Active Datapath for Branch and BSR Branch on equal Zero Test beq PC Ra 0 PC 4 disp 4 PC 4 0x39 ra 31 26 25 21 Instr disp datIn 20 0 20 0 IF Instruction fetch P C IR IMemory PC incrPC PC 4 Data Mem Xtnd 2 25 21 regA 20 16 regB Instr Mem datW datOut datA regW ALU aluB datB …
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