VO L 1 0 N O 1 5 Digital MIPS Add Multimedia Extensions M IC R O P Digital Focuses on Video MIPS on 3D Graphics Vendors Debate Differences ES S O OC R R by Linley Gwennap FORUM Support for multimedia data types has become nearly pervasive as Alpha and MIPS have joined the throng of instruction set architectures with multimedia extensions At last month s Microprocessor Forum Digital announced its motion video instructions MVI which will first appear in the 21164PC and 21264 processors next year Also at the conference MIPS Technologies rolled out two sets of multimedia extensions The first MIPS V supports parallel floating point operations and will mainly benefit 3D graphics A separate set of instructions called MDMX MIPS digital media extensions provides broader support for parallel integer operations The MIPS V extensions allow two single precision operands to be stored in a double precision floating point register using the new paired single PS format Several new instructions can then operate on this data in parallel effectively doubling performance in this mode Since many 3D graphics applications as well as some scientific software use single precision FP most of these applications could see a boost from MIPS V The company would not discuss what processors will implement MIPS V but we expect the followon to the R10000 code named H1 will do so MDMX also known as Mad Max is an optional set of instructions similar to Intel s MMX see 100301 PDF in that they define a set of media registers that is mapped onto the FP registers new data types that store 8 and 16 bit data in parallel in the media registers and instructions that operate on this data in parallel MDMX s unique twist is its 192 bit accumulator that allows integer multiplication and accumulation to occur without any overflows or loss of precision Digital s additions are more spare in keeping with the minimalist nature of the Alpha instruction set Digital engineer Pete Bannon argued that current Alpha processors are fast enough to handle relatively simple tasks like audio mix ing and video decoding without any instruction set extensions so why add new instructions that could slow the decoders or the execution units To meet a 2 ns cycle time simplicity is a requirement The new instructions are designed to speed video encoding a much harder problem without slowing the CPU on other tasks These two vendors join HP Intel and Sun in adding multimedia extensions to their instruction sets Large performance gains on multimedia applications coupled with the relatively small incremental hardware cost have led to this widespread adoption Of the major desktop processors only PowerPC now lacks such extensions an incredible oversight given Apple s focus on multimedia MIPS V Boosts FP Performance Most of these extensions aim to improve performance when handling 8 and 16 bit integers These data types are common in audio video and graphics applications yet traditional ALUs can operate on only one integer at a time With most processors now implementing 64 bit data paths up to seven eighths of this data path is wasted when operating on small integers Packing four or eight small integers into a single 64 bit register and operating on them in parallel using a SIMD single instruction multiple data approach greatly increases throughput MIPS realized a similar opportunity exists on the floating point side yet no other vendor has moved to seize it Modern microprocessors are optimized to handle doubleprecision floating point data meaning that a 64 bit data path exists in the FPU Yet single precision floating point data is common in many applications including 3D graphics and signal processing these applications waste half of the FP data path The same SIMD approach can double throughput on single precision data MIPS V does just that The new PS format pairs two single precision values in each FP register Table 1 lists the At the Microprocessor Forum several instruction set architects gathered to discuss extensions for multimedia processing including l to r Pete Bannon of Digital Earl Killian of MIPS Technologies Ruby Lee of HP Uri Weiser of Intel and Marc Tremblay of Sun Microelectronics At right is moderator Linley Gwennap of MicroDesign Resources MICRODESIGN RESOURCES NOVEMBER 18 1996 MICROPROCESSOR REPORT 2 D I G I TA L M I P S A D D M U LT I M E D I A E X T E N S I O N S Modified Instructions ADD SUB MUL ABS MOV NEG Basic computational operations MADD MSUB NMADD NMSUB Multiply add subtract Parallel compare C cond Conditional move MOVF MOVT New Instructions LUXC1 SUXC1 ALNV PLL PLU PUL PUU CVT PS S Load 8 bytes without alignment Realign data Rearrange PS data Convert to from PS format Table 1 MIPS V modifies existing FP instructions to use the new paired single PS data type and adds a few new instructions for packing rearranging and unpacking PS data existing FP instructions that accept PS operands in MIPS V these include the basic arithmetic operations Note that the product of two single precision operands is still a singleprecision value with the exponent adjusted accordingly Thus multiplying two paired single operands results in a paired single product The table also lists a few new instructions in MIPS V The LUXC1 and SUXC1 instructions don t try to pronounce them load and store 64 bits at a time regardless of the alignment of the address that is the lowest three bits of the address are simply ignored These FP instructions help load pairs of single precision operands when the operands are part of a vector that is not aligned to a 64 bit boundary The ALNV instruction can then properly align the data The Pxx instructions are useful for copying the upper or lower half of a PS value to the upper or lower half of another PS value Finally a new convert CVT instruction creates a PS value from two single precision values This instruction takes two FP registers as source operands These instructions will add a small amount of circuitry particularly when compared with the size of a high performance double precision FPU yet they will provide a big performance boost on some frequently used algorithms such as fast Fouri r transform FFT and matrix multiplication MDMX Goes Beyond Intel s MMX The basic features of MIPS MDMX are similar to those of Intel s MMX MDMX creates a new set of 32 media registers each 64 bits wide To reduce storage requirements they are mapped onto the floating point registers Intel uses the same strategy for its MMX registers but since
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