©MICRODESIGN RESOURCES NOVEMBER 18, 1996 MICROPROCESSOR REPORTVOL. 10, NO. 15by Linley GwennapSupport for multimedia data types has be-come nearly pervasive, as Alpha and MIPShave joined the throng of instruction-setarchitectures with multimedia extensions. At last month’sMicroprocessor Forum, Digital announced its motion-videoinstructions (MVI), which will first appear in the 21164PCand 21264 processors next year. Also at the conference, MIPSTechnologies rolled out two sets of multimedia extensions.The first, MIPS V, supports parallel floating-point opera-tions and will mainly benefit 3D graphics. A separate set ofinstructions called MDMX (MIPS digital media extensions)provides broader support for parallel integer operations.The MIPS V extensions allow two single-precisionoperands to be stored in a double-precision floating-pointregister using the new paired-single (PS) format. Several newinstructions can then operate on this data in parallel, effec-tively doubling performance in this mode. Since many 3Dgraphics applications, as well as some scientific software, usesingle-precision FP, most of these applications could see aboost from MIPS V. The company would not discuss whatprocessors will implement MIPS V, but we expect the follow-on to the R10000, code-named H1, will do so.MDMX, also known as Mad Max, is an optional set ofinstructions similar to Intel’s MMX (see 100301.PDF) in thatthey define a set of media registers that is mapped onto theFP registers, new data types that store 8- and 16-bit data inparallel in the media registers, and instructions that operateon this data in parallel. MDMX’s unique twist is its 192-bitaccumulator that allows integer multiplication and accumu-lation to occur without any overflows or loss of precision.Digital’s additions are more spare, in keeping with theminimalist nature of the Alpha instruction set. Digital engi-neer Pete Bannon argued that current Alpha processors arefast enough to handle relatively simple tasks like audio mix-ing and video decoding without any instruction-set exten-sions, so why add new instructions that could slow thedecoders or the execution units? To meet a 2-ns cycle time,simplicity is a requirement. The new instructions are de-signed to speed video encoding, a much harder problem,without slowing the CPU on other tasks.These two vendors join HP, Intel, and Sun in addingmultimedia extensions to their instruction sets. Large per-formance gains on multimedia applications, coupled withthe relatively small incremental hardware cost, have led tothis widespread adoption. Of the major desktop processors,only PowerPC now lacks such extensions, an incredible over-sight given Apple’s focus on multimedia.MIPS V Boosts FP PerformanceMost of these extensions aim to improve performance whenhandling 8- and 16-bit integers. These data types are com-mon in audio, video, and graphics applications, yet tradi-tional ALUs can operate on only one integer at a time. Withmost processors now implementing 64-bit data paths, up toseven-eighths of this data path is wasted when operating onsmall integers. Packing four or eight small integers into a sin-gle 64-bit register and operating on them in parallel using aSIMD (single instruction, multiple data) approach greatlyincreases throughput.MIPS realized a similar opportunity exists on the float-ing-point side, yet no other vendor has moved to seize it.Modern microprocessors are optimized to handle double-precision floating-point data, meaning that a 64-bit datapath exists in the FPU. Yet single-precision floating-pointdata is common in many applications, including 3D graphicsand signal processing; these applications waste half of the FPdata path. The same SIMD approach can double throughputon single-precision data.MIPS V does just that. The new PS format pairs twosingle-precision values in each FP register. Table 1 lists theDigital, MIPS Add Multimedia ExtensionsDigital Focuses on Video, MIPS on 3D Graphics; Vendors Debate DifferencesAt the Microprocessor Forum, several instruction-set architects gathered to discuss extensions for multimedia processing, including (l to r)Pete Bannon of Digital, Earl Killian of MIPS Technologies, Ruby Lee of HP, Uri Weiser of Intel, and Marc Tremblay of Sun Microelectronics.At right is moderator Linley Gwennap of MicroDesign Resources.MICROPROCESSORFORUM©MICRODESIGN RESOURCES NOVEMBER 18, 1996 MICROPROCESSOR REPORT2 DIGITAL, MIPS ADD MULTIMEDIA EXTENSIONS VOL. 10, NO. 15existing FP instructions that accept PS operands in MIPS V;these include the basic arithmetic operations. Note that theproduct of two single-precision operands is still a single-precision value, with the exponent adjusted accordingly.Thus, multiplying two paired-single operands results in apaired-single product.The table also lists a few new instructions in MIPS V.The LUXC1 and SUXC1 instructions (don’t try to pronouncethem!) load and store 64 bits at a time regardless of the align-ment of the address; that is, the lowest three bits of theaddress are simply ignored. These FP instructions help loadpairs of single-precision operands when the operands arepart of a vector that is not aligned to a 64-bit boundary. TheALNV instruction can then properly align the data.The Pxx instructions are useful for copying the upper orlower half of a PS value to the upper or lower half of anotherPS value. Finally, a new convert (CVT) instruction creates aPS value from two single-precision values. This instructiontakes two FP registers as source operands.These instructions will add a small amount of circuitry,particularly when compared with the size of a high-perfor-mance double-precision FPU, yet they will provide a big per-formance boost on some frequently used algorithms, such asfast Fouriér transform (FFT) and matrix multiplication.MDMX Goes Beyond Intel’s MMXThe basic features of MIPS’ MDMX are similar to those ofIntel’s MMX. MDMX creates a new set of 32 media registers,each 64 bits wide. To reduce storage requirements, they aremapped onto the floating-point registers. Intel uses the samestrategy for its MMX registers, but since x86 has only eightFP registers, there are also only eight MMX registers. MDMXadds a set of eight single-bit condition flags, which map ontothe MIPS FP condition flags.The new registers support two data formats: oct byte(OB) and quad half (QH). For the jargon-impaired, the for-mer refers to eight 8-bit values packed into a single 64-bitregister, while the latter
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