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CMU CS 15740 - lecture

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Page 1Multiprocessor InterconnectionNetworksCS 740November 13, 2002Topics• Network design issues• Network TopologySlides from TCM & CSCS 740 F’01–2 –Networks• How do we move data between processors?• Design Options:• Topology• Routing• Physical implementationPage 2CS 740 F’01–3 –Evaluation Criteria:•Latency• Bisection Bandwidth• Contention and hot-spot behavior• Partitionability• Cost and scalability• Fault toleranceCS 740 F’01–4 –Buses• Simple and cost-effective for small-scale multiprocessors• Not scalable (limited bandwidth; electrical complications)P PPBusPage 3CS 740 F’01–5 –Crossbars• Each port has link to every other port+ Low latency and high throughput- Cost grows as O(N^2) so not very scalable. - Difficult to arbitrate and to get all data lines into and out of a centralized crossbar.• Used in small-scale MPs (e.g., C.mmp) and as building block for other networks (e.g., Omega).PPPPM M M MCrossbarCS 740 F’01–6 –Rings• Cheap: Cost is O(N).• Point-to-point wires and pipelining can be used to make them very fast.+ High overall bandwidth-High latency O(N)• Examples: KSR machine, HectorP PPP P PRingPage 4CS 740 F’01–7 –Trees• Cheap: Cost is O(N).• Latency is O(logN).• Easy to layout as planar graphs (e.g., H-Trees).• For random permutations, root can become bottleneck.• To avoid root being bottleneck, notion of Fat-Trees(used in CM-5)H-TreeFat TreeCS 740 F’01–8 –Hypercubes• Also called binary n-cubes. # of nodes = N = 2^n.• Latency is O(logN); Out degree of PE is O(logN)• Minimizes hops; good bisection BW; but tough to layout in 3-space• Popular in early message-passing computers (e.g., inteliPSC, NCUBE)• Used as direct network ==> emphasizes locality0-D 1-D 2-D 3-D4-DPage 5CS 740 F’01–9 –Multistage LogarithmicNetworksKey Idea: have multiple layers of switches between destinations.• Cost is O(NlogN); latency is O(logN); throughput is O(N).• Generally indirect networks. • Many variations exist (Omega, Butterfly, Benes, ...).• Used in many machines: BBN Butterfly, IBM RP3, ...CS 740 F’01–10 –Omega Network• All stages are same, so can use recirculating network.• Single path from source to destination.• Can add extra stages and pathways to minimize collisions and increase fault tolerance.• Can support combining. Used in IBM RP3.000001010011100101110111000001010011100101110111Omega Net wor kPage 6CS 740 F’01– 11 –Butterfly Network000001010011100101110111000001010011100101110111Butterfly Networksplit on MSBsplit on LSB• Equivalent to Omega network. Easy to see routing of messages.• Also very similar to hypercubes (direct vs. indirect though).• Clearly see that bisection of network is (N / 2) channels.• Can use higher-degree switches to reduce depth. CS 740 F’01–12 –k-ary n-cubes• Generalization of hypercubes (k-nodes in a string)• Total # of nodes = N = k^n.• k > 2 reduces # of channels at bisection, thus allowing for wider channels but more hops.4-ary 3-cubePage 7CS 740 F’01–13 –Real World 2D mesh1824 node Paragon: 16 x 114 arrayCS 740 F’01–14 –Advantages of Low-Dimensional NetsWhat can be built in VLSI is often wire-limitedLDNs are easier to layout:• more uniform wiring density (easier to embed in 2-D or 3-D space)• mostly local connections (e.g., grids)Compared with HDNs (e.g., hypercubes), LDNshave:• shorter wires (reduces hop latency)• fewer wires (increases bandwidth given constant bisection width)– increased channel width is the major reason why LDNs win!LDNs have better hot-spot throughput• more pins per node than HDNsPage 8CS 740 F’01–15 –Embeddings in two dimensionsEmbed multiple logical dimension in one physical dimension using long wires6 x 3 x 2CS 740 F’01–16 –RoutingRecall: routing algorithm determines • which of the possible paths are used as routes• how the route is determined• R: N x N -> C, which at each switch maps the destination node ndto the next channel on the routeIssues:• Routing mechanism–arithmetic– source-based port select–table driven– general computation• Properties of the routes• Deadlock freePage 9CS 740 F’01–17 –Routing Mechanismneed to select output port for each input packet• in a few cyclesReduce relative address of each dimension in order• Dimension-order routing in k-ary d-cubes• e-cube routing in n-cubeCS 740 F’01–18 –Routing Mechanism (cont)Source-based• message header carries series of port selects• used and stripped en route•CRC? Packet Format?• CS-2, Myrinet, MIT ArticTable-driven• message header carried index for next port at next switch–o = R[i]• table also gives index for following hop– o, I’ = R[i ]• ATM, HPPIP0P1P2P3Page 10CS 740 F’01–19 –Properties of Routing AlgorithmsDeterministic• route determined by (source, dest), not intermediate state (i.e. traffic)Adaptive• route influenced by traffic along the wayMinimal• only selects shortest pathsDeadlock free• no traffic pattern can lead to a situation where no packets mover forwardCS 740 F’01– 20 –Deadlock FreedomHow can it arise?• necessary conditions:– shared resource– incrementally allocated– non-preemptible• think of a channel as a shared resource that is acquired incrementally– source buffer then dest. buffer– channels along a routeHow do you avoid it?• constrain how channel resources are allocated• ex: dimension orderHow do you prove that a routing algorithm is deadlock freePage 11CS 740 F’01–21 –Proof TechniqueResources are logically associated with channelsMessages introduce dependences between resources as they move forwardNeed to articulate possible dependences between channelsShow that there are no cycles in Channel Dependence Graph• find a numbering of channel resources such that every legal route follows a monotonic sequence=> no traffic pattern can lead to deadlockNetwork need not be acyclic, only channel dependence graphCS 740 F’01– 22 –ExamplesWhy is the obvious routing on X deadlock free?• butterfly?• tree?• fat tree?Any assumptions about routing mechanism? amount of buffering?What about wormhole routing on a


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CMU CS 15740 - lecture

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