Alpha ALU Instructions Advanced Pipelining CS740 RR type instructions addq subq xor bis cmplt rc ra funct rb Op ra rb 000 0 funct rc 31 26 October 30 2007 25 21 20 16 15 13 12 11 5 Topics Op ra ib 1 funct rc 31 26 25 21 20 13 12 11 5 4 0 Encoding ib is 8 bit unsigned literal Operation Op field Data Hazards Stalling and Forwarding Systematic testing of hazard handling logic Control Hazards Stalling Predict not taken Exceptions Multicycle Instructions funct field addq subq bis xor cmoveq 0x10 0x10 0x11 0x11 0x11 0x20 0x29 0x20 0x40 0x24 cmplt 0x11 0x4D 2 Pipelined ALU Instruction Datapath IF ID instruction fetch instruction decode register fetch IF ID MEM EX EX MEM Data Hazards in Alpha Pipeline Registers read in ID and written in WB Must resolve conflict between instructions competing for register array Generally do write back in first half of cycle read in second But what about intervening instructions E g suppose initially 2 is zero write back MEM WB Adata Instr datIn Data Mem P C 25 21 regA 20 16 regB Instr Mem datW 20 13 4 0 4 regW CS 740 F 07 Problem WB memory access execute ID EX datOut datA Reg Array datB addr aluA ALU ALUout IF ID EX 2 3 4 5 6 aluB Wdest IncrPC CS 740 F 07 addq 2 0 3 M WB IF ID EX M WB IF ID EX Time addq 2 0 4 M WB IF ID EX 4 Page 1 addq 31 63 2 M WB IF ID EX Wdata 3 4 0 RI type instructions addq subq xor bis cmplt rc ra funct ib M WB addq 2 0 5 addq 2 0 6 2 written CS 740 F 07 Idea Detecting Dependencies Handling Hazards by Stalling Transfer Stall Bubble Pipe Register Operation 5 P C Instr Mem 4 IF ID Instr Mem Reg File Transfer EX EX MEM Adata MEM WB datIn regA 20 16 regB datW datA Reg Array regW datOut addr aluA ALU ALUout aluB datB Wdest W Dst IncrPC W Dst W Dst Write WriteDests Dests Wdata Next Current State State Pending Register Reads Pending Register Writes By instruction in ID ID in IR 25 21 Operand A ID in IR 20 16 Operand B Only for RR EX in WDst Destination register of instruction in EX MEM in WDst Destination register of instruction in MEM 6 CS 740 F 07 Stalling for Data Hazards Stall Control Bubble 25 21 4 0 Implementing Stalls Stall ID EX Data Mem 20 13 CS 740 F 07 Stall Read ReadSources Sources Instr Delay instruction until hazard eliminated Put bubble into pipeline Dynamically generated NOP Transfer normal operation indicates should transfer next state to current Stall indicates that current state should not be changed Bubble indicates that current state should be set to 0 Stage logic designed so that 0 is like NOP Other conventions possible IF ID Operation Transfer First instruction progresses unimpeded Second waits in ID until first hits WB Third waits in IF until second allowed to progress MEM Data Mem IF ID EX 2 3 4 5 6 Stall Control Logic Determines which stages to stall bubble or transfer on next update Rule addq 31 63 2 M WB IF ID ID ID EX addq 2 0 3 M WB IF IF IF ID EX IF ID EX M WB IF ID EX Stall in ID if either pending read matches either pending write Also stall IF bubble EX Time Effect addq 2 0 4 M WB M WB addq 2 0 5 addq 2 0 6 2 written Instructions with pending writes allowed to complete before instruction allowed out of ID 7 CS 740 F 07 8 Page 2 CS 740 F 07 Forwarding Bypassing Observations on Stalling Good Observation Relatively simple hardware Only penalizes performance when hazard exists ALU data generated at end of EX Steps through pipe until WB ALU data consumed at beginning of EX Bad Idea As if placed NOPs in code Except that does not waste instruction memory Expedite passing of previous instruction result to ALU By adding extra data pathways and control Reality Some problems can only be dealt with by stalling Instruction cache miss Data cache miss Otherwise want technique with better performance 9 CS 740 F 07 10 Forwarding for ALU Instructions IF ID ID EX EX MEM Adata Instr P C Instr Mem regA 20 16 regB datW 20 13 20 16 4 0 4 IncrPC 25 21 Bypassing Possibilities MEM WB IF ID regW datA datOut addr aluA Reg Array ALU P C ALUout B Src W Dst W Dst ALU input A Register EX in ASrc ALU input B Register EX in BSrc 11 regA regB datW 4 0 W Dst A Src 4 IncrPC 25 21 regW datA datIn datOut addr aluA Reg Array ALU ALUout aluB datB B Src W Dst Wdest W Dst W Dst A Src EX EX Operand Sources Wdata EX EX From instruction that just finished EX MEM in ALUout Pending write to MEM in WDst WB in ALUout Pending write to WB in WDst MEM WB Data Mem 20 16 20 16 Wdest EX MEM Adata 25 21 20 13 Wdata Operand Destinations Instr Mem aluB datB ID EX Instr datIn Data Mem 25 21 CS 740 F 07 MEM EX MEM EX From instruction that finished EX two cycles earlier CS 740 F 07 12 Page 3 CS 740 F 07 Load Store Instructions Bypassing Data Hazards Load Ra Mem Rb offset Operation First instruction progresses down pipeline When in MEM forward result to second instruction in EX EX EX forwarding When in WB forward result to third instruction in EX MEM EX forwarding IF ID EX 2 3 4 5 6 IF ID EX IF ID EX M WB IF ID EX Time M WB Op ra 31 26 25 21 Load Store addq 2 0 6 rb offset 20 16 15 0 Mem Data DMemory ALUOutput DMemory ALUOutput A WB Write back Load CS 740 F 07 Register IR 25 21 Mem Data 14 Analysis of Data Transfers CS 740 F 07 Some Hazards with Loads Stores Data Sources Data Generated by Load Available after EX ALU Result Reg Reg Result Available after MEM Read Data Load result ALU Data Reg Reg Result passing through MEM stage Load Store Data ALU A input Need in EX Reg Reg or Reg Immediate Operand ALU B input Need in EX Reg Reg Operand Load Store Base Write Data Need in MEM Store Data Data Generated by Store Store Load Data ldq 1 8 2 stq 1 8 2 stq 1 16 2 ldq 3 8 2 Data Destinations Load ALU ldq 1 8 2 addq 2 1 2 ldq 1 8 2 CS 740 F 07 16 Page 4 Not a concern for us Data Generated by ALU ALU Store or Load Addr addq 1 3 2 stq 3 8 2 Load Store or Load Addr stq 2 16 1 15 15 0 MEM Memory addq 2 0 5 2 written 13 offset Store …
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