Intel’s P6 Uses Decoupled Superscalar DesignNot Your Grandfather’s Pentiumx86 Instructions Translate to Micro-opsFigure 1. The P6 combines an in-order front end with …Out-of-Order Engine Drives PerformanceNonblocking Caches Reduce StallsTable 1. P6 floating-point latencies are similar to Pentium’s …Figure 2. The P6 CPU and L2 cache are combined …Deep Pipeline Speeds Clock RateTable 2. The fast nonblocking L2 cache …Figure 3. In the best case, instructions can flow …Branch Prediction Accuracy Is CriticalConditional Move AddedP6 Bus Allows Glueless MPFigure 4. The P6 CPU measures 17.5 ¥ 17.5 mm …Another Big, Power-Hungry CPUImproving System PerformanceTable 3. The P6 feature set stacks up well against top x86 competitors …by Linley GwennapIntel’s forthcoming P6 processor (see cover story) isdesigned to outperform all other x86 CPUs by a signifi-cant margin. Although it shares some design techniqueswith competitors such as AMD’s K5, NexGen’s Nx586,and Cyrix’s M1, the new Intel chip has several importantadvantages over these competitors.The P6’s deep pipeline eliminates the cache-accessbottlenecks that restrict its competitors to clock speedsof about 100 MHz. The new CPU is designed to run at133 MHz in its initial 0.5-micron BiCMOS implementa-tion; a 0.35-micron version, due next year, could pushthe speed as high as 200 MHz.In addition, the Intel design uses a closely coupledsecondary cache to speed memory accesses, a criticalissue for high-frequency CPUs. Intel will combine the P6CPU and a 256K cache chip into a single PGA package,reducing the time needed for data to move from thecache to the processor.Like some of its competitors, the P6 translates x86instructions into simple, fixed-length instructions thatIntel calls micro-operations or uops (pronounced “you-ops”). These uops are then executed in a decoupled su-perscalar core capable of register renaming and out-of-order execution. Intel has given the name “dynamicexecution” to this particular combination of features,which is neither new nor unique, but highly effective inincreasing x86 performance.The P6 also implements a new system bus with in-creased bandwidth compared to the Pentium bus. Thenew bus is capable of supporting up to four P6 processorswith no glue logic, reducing the cost of developing andbuilding multiprocessor systems. This feature set makesthe new processor particularly attractive for servers; itwill also be used in high-end desktop PCs and, eventu-ally, in mainstream PC products.Not Your Grandfather’s PentiumWhile Pentium’s microarchitecture carries a dis-tinct legacy from the 486, it is hard to find a trace of Pen-tium in the P6. The P6 team threw out most of the designtechniques used by the 486 and Pentium and startedfrom a blank piece of paper to build a high-performancex86-compatible processor.The result is a microarchitecture that is quite radi-cal compared with Intel’s previous x86 designs, but onethat draws from the same bag of tricks as competitors’x86 chips. To this mix, the P6 adds high-performancecache and bus designs that allow even large programs tomake good use of the superscalar CPU core.As Figure 1 (see below) shows, the P6 can be dividedinto two portions: the in-order and out-of-order sections.Instructions start in order but can be executed out oforder. Results flow to the reorder buffer (ROB), whichputs them back into the correct order. Like AMD’s K5(see 081401.PDF), the P6 uses the ROB to hold resultsthat are generated by speculative and out-of-order in-structions; if it turns out that these instructions shouldnot have been executed, their results can be flushed fromthe ROB before they are committed.The performance increase over Pentium comeslargely from the out-of-order execution engine. In Pen-tium, if an instruction takes several cycles to execute,due to a cache miss or other long-latency operation, theentire processor stalls until that instruction can proceed.In the same situation, the P6 will continue to executesubsequent instructions, coming back to the stalled in-struction once it is ready to execute. Intel estimates thatthe P6, by avoiding stalls, delivers 1.5 SPECint92 perMHz, about 40% better than Pentium.x86 Instructions Translate to Micro-opsThe P6 CPU includes an 8K instruction cache thatis similar in structure to Pentium’s. On each cycle, it candeliver 16 aligned bytes into the instruction byte queue.Unlike Pentium, the P6 cache cannot fetch an unalignedcache line, throttling the decode process when poorlyaligned branch targets are encountered. Any hiccups inthe fetch stream, however, are generally hidden by thedeep queues in the execution engine.The instruction bytes are fed into three instructiondecoders. The first decoder, at the front of the queue, canhandle any x86 instruction; the others are restricted toonly simple (e.g., register-to-register) instructions. In-structions are always decoded in program order, so if aninstruction cannot be handled by a restricted decoder,neither that instruction nor any subsequent ones can bedecoded on that cycle; the complex instruction will even-tually reach the front of the queue and be decoded by thegeneral decoder.Assuming that instruction bytes are available, atleast one x86 instruction will be decoded per cycle, butmore than one will be decoded only if the second (andthird) instructions fall into the “restricted” category.Intel refused to list these instructions, but they do not in-clude any that operate on memory. Thus, the P6’s abilityto execute more than one x86 instruction per cycle reliesMICROPROCESSOR REPORTIntel’s P6 Uses Decoupled Superscalar Design Vol. 9, No. 2, February 16, 1995 © 1995 MicroDesign ResourcesIntel’s P6 Uses Decoupled Superscalar DesignNext Generation of x86 Integrates L2 Cache in Package with CPUon avoiding long sequences of complex instructions or in-structions that operate on memory.The decoders translate x86 instructions into uops.P6 uops have a fixed length of 118 bits, using a regularstructure to encode an operation, two sources, and a des-tination. The source and destination fields are each wideenough to contain a 32-bit operand. Like RISC instruc-tions, uops use a load/store model; x86 instructions thatoperate on memory must be broken into a load uop, anALU uop, and possibly a store uop.The restricted decoders can produce only one uopper cycle (and thus accept only instructions that trans-late into a single uop). The generalized decoder is
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