Vector Architectures Past Present and Future James E Smith Roger Espasa Mateo Valero Computer U Politbcnica Architecture Dept Dept of Electrical University de Catalunya Barcelona Although Abstract characteristics Vector architectures have long been the of choice for building supercomputers They first appeared in the early aeventies and had a long period of unquestioned dominance from the time the CRAY 1 was introduced in 1976 until the the in 1991 They still have a appearance of killer micros their foothold in the supercomputer marketplace although continued viability in the face of micro baaed parallel aystens is being seriously questioned We present a brief hiatory of supercomputing and discuss the merits of vector architectures Then we relate the advantages of vector architectures with current trends in computer system and device technology Although the viability of vector supercomputers is indeed questionable largely because of coat issues we argue that vector architectures have a long future ahead of them with new applications and commodity implementations Vector instruction sets have many fundamental advantages and deserve serious consideration for implementation in next generation computer systems where graphics and other multimedia applications will abound A Brief History The floating Roots 1 2 point processing arithmetic they had many The 6600 and 7600 were They implemented and were constructed 60 bit of what at The Rise of Vector Supercomputers The first two vector supercomputers appeared in the early 1970s The two machines were remarkably similar One was developed at Texas Instruments the TI ASC 3 It was Texas Instruments only venture into large scale computers and only a handful were ever sold The other was developed at Control Data Corporation the STAR loo Only a few STAR loos sold as well but it was the beginning of a series of vector machines developed at CDC over the years The ASC and the STAR 100 were centered around a very high powered vector unit that took streams of operands from memory operated on them then sent the result streams back to memory all in a single instruction The primary job of the scalar unit was to service the vector unit to do bookkeeping computation and do any scalar code that couldn t be done with vectors Because they were memoryto memory vector machines they were built with very advanced high bandwidth memory systems A pipeline that stretched from memory through the processor and back to memory was very long and took many clock cycles to fill but once it was filled the throughput was tremendous Both machines used instruction sets that would be categorized as CISC today For example in a single vector instruction the ASC could do a complete matrix multiplication STAR 100 instructions operated on arrays of numerical data and on strings of characters and bits STAR stood for STring ARray The STAR 100 also had features to support sparse matrix operations Many of the instructions had so much semantic content it is doubtful that a compiler would be able to use them as targets for automatic vectorization they could most easily be used in assemblycoded library routines Although they are remembered mostly for their ultimately unsuccessful memory to memory architectures the ASC and STAR 100 also contained several innovations that have lived on until today One example is the method they used for implementing conditional operations i e bit masks for control Data movement operations implemented with of Supercomputing Although the term wasn t coined until later supercomputing probably began with the Control Data 6600 and 7600 l The 6600 was rolled out in 1963 and the 7600 in 1969 They were scalar machines and were the first to use RISC instruction sets James Thornton and Seymour Cray were co developers of the 6600 Thornton went on to develop the STAR 100 a while Cray continued with the 7600 and the unfinished 8600 before leaving CDC to found Cray Research This work under contract tThis work of supercomputers the time were exotic technologies Their clock cycles and overall performance levels were far superior to their closest competition They had large memory capacity and very high I O bandwidth And their price tag was very high many millions of dollars in 1960s dollars of Supercomputing Six Hundreds they were scalar machines focused on numerical To better understand vector supercomputers we begin with a brief history And to provide broader perspective we consider supercomputers in general we don t restrict ourselves to vector machines 1 1 WI 53706 jes ece wisc edu http www ac upc es hpc 1 Engr of Wisconsin Madison Madison roger mateo ac upc es Computer was supported by the Ministry of Education of Spain 0429 95 and by the CEPBA was supported in part by NSF Grant MIP 9505853 Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page To copy otherwise to republish to post on servers or to redistribute to lists requires prior specific permission and or a fee ICS 98 Melbourne Australia Copyright ACM 1998 0 89791 998 x 98 7 5 00 425 introduced a line of parallel vector computers Using their expertise in chip technology and emphasizing multiple vector pipelines per processor all three manufacturers succeeded in developing very fast vector machines As our later graphs will show the vector processors used in these machines are the most powerful uniprocessors ever built see the NEC SX 3 at 5 5 Gflops for example Following the success of the big iron vendors in the early 1980 s several start up companies designed and sold minisupercomputers These were small vector machines with slower clocks than the big supercomputers and less processing power per vector unit The most successful example was Convex Computer Corporation It s first machine the C l was introduced in 1985 with a clock rate of 1OMhz much slower than a contemporary 16OMhz SX 2 The selling point of these mini supers was that they provided limited supercomputing capabilities at a much more affordable price typically 0 5201 million dollars versus 5to30 million stride and gather scatter memory accesses are still used today They could split their pipelines to double performance on 32 bit dat a The ASC could be upgraded by adding additional vector pipelines up to a total of four And the STAR
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