Basic Pipelining September 20 2000 Topics Objective Instruction formats Instruction processing Principles of pipelining Inserting pipe registers Objectiv e Design Processor for Alpha Subset Interesting but not overwhelming quantity High level functional blocks Initial Design One instruction at a time Single cycle per instruction Follows H P Ch 3 1 Chs 5 1 5 3 in undergrad version of text Refined Design 5 stage pipeline Similar to early RISC processors Follows H P Ch 3 2 Chs 6 1 6 7 in undergrad version of text Goal approach 1 cycle per instruction but with shorter cycle time 2 CS 740 F 00 Alpha Arithmetic RR type instructions addq subq xor bis cmplt Instructions Op ra 31 26 25 21 rb 20 16 000 0 funct rc 15 13 12 11 5 4 0 rc ra funct rb RI type instructions addq subq xor bis cmplt rc ra funct ib Op ra ib 1 funct rc 31 26 25 21 20 13 Encoding ib is 8 bit unsigned literal Operation Op field 3 12 11 5 4 0 funct field addq subq bis xor cmoveq 0x10 0x10 0x11 0x11 0x11 0x20 0x29 0x20 0x40 0x24 cmplt 0x11 0x4D CS 740 F 00 Alpha Load Store Load Ra Mem Rb offset Instructions Store Mem Rb offset Ra Op ra rb offset 31 26 25 21 20 16 15 0 Encoding offset is 16 bit signed offset Operation Op field ldq stq 4 0x29 0x2D CS 740 F 00 Branch Cond Branch PC Cond Ra PC 4 disp 4 PC 4 Instructions Op ra disp 31 26 25 21 20 0 Encoding disp is 21 bit signed displacement Operation Op field Cond beq bne 0x39 0x3D Ra 0 Ra 0 Branch Subroutine br bsr Ra PC 4 PC PC 4 disp 4 Op ra disp 31 26 25 21 20 0 Operation br bsr 5 Op field 0x30 0x34 CS 740 F 00 Transfers of jmp jsr ret Ra PC 4 PC Rb Control 0x1A ra rb Hint 31 26 25 21 20 16 15 0 Encoding High order 2 bits of Hint encode jump type Remaining bits give information about predicted destination Hint does not affect functionality Jump Type Hint 15 14 jmp jsr ret 00 01 10 call pal 0x00 Number 31 26 25 0 Use as halt instruction 6 CS 740 F 00 0x0 40220403 Instruction Encoding addq r1 r2 r3 0x4 4487f805 xor r4 0x3f r5 0x8 a4c70abc ldq r6 2748 r7 0xc b5090123 stq r8 291 r9 0x10 e47ffffb beq r3 0 0x14 d35ffffa bsr r26 0 r31 0x18 6bfa8001 ret r31 r26 1 0x1c 000abcde call pal 0xabcde Object Code Instructions encoded in 32 bit words Program behavior determined by bit encodings Disassembler simply converts these words to readable instructions 7 CS 740 F 00 0x0 40220403 Decoding Examples addq r1 r2 r3 0x8 a4c70abc 4 0 2 2 0 4 0 3 0100 0000 0010 0010 0000 0100 0000 0011 10 01 02 0x10 e47ffffb beq 20 03 r3 0 e 4 7 f f f f b 1110 0100 0111 1111 1111 1111 1111 1011 39 03 Target 8 1ffffb 510 16 Current PC 4 Increment 4 5 Disp 0 ldq r6 2748 r7 a 4 c 7 0 a b c 1010 0100 1100 0111 0000 1010 1011 1100 29 06 07 0x18 6bfa8001 0abc 274810 ret r31 r26 1 6 b f a 8 0 0 1 0110 1011 1111 1010 1000 0000 0000 0001 1a 1f 1a 2 3110 2610 CS 740 F 00 IF Datapa th EX ID MEM WB instruction fetch instruction decode execute register fetch address calculation memory access write back Zero Test Instr 15 0 20 0 P C Instr Mem regA 20 16 regB 25 21 Data Mem Xtnd 2 datW 4 0 IncrPC Xtnd 25 21 20 13 4 datIn regW datA Reg Array datB addr aluA datOut ALU aluB Wdest Wdata 9 CS 740 F 00 Hardware Units Storage Instruction Memory Fetch 32 bit instructions Data Memory Load store 64 bit data Register Array Storage for 32 integer registers Two read ports can read two registers at once Single write port Functional Units 4 Xtnd ALU Zero Test 10 PC incrementer Sign extender Arithmetic and logical instructions Detect whether operand 0 CS 740 F 00 RR type RR type instructions addq subq xor bis cmplt rc ra funct rb instructions Op ra rb 000 0 funct rc 31 26 25 21 20 16 15 13 12 11 5 4 0 IF Instruction fetch IR IMemory PC PC PC 4 ID Instruction decode register fetch A Register IR 25 21 B Register IR 20 16 Ex Execute ALUOutput A op B MEM Memory nop WB Write back Register IR 4 0 ALUOutput 11 CS 740 F 00 Active Datapath for RR RI Instr datIn Data Mem P C Instr Mem 25 21 regA 20 16 regB datW 20 13 regW datA Reg Array datB aluA ALU aluB 4 0 4 datOut addr Wdest IncrPC Wdata ALU Operation Input B selected according to instruction type datB for RR IR 20 13 for RI ALU function set according to operation type 12 Write Back To Rc CS 740 F 00 RI type RI type instructions addq subq xor bis cmplt rc ra funct ib instructions Op ra ib 1 funct rc 31 26 25 21 20 13 12 11 5 4 0 IF Instruction fetch IR IMemory PC PC PC 4 ID Instruction decode register fetch A Register IR 25 21 B IR 20 13 Ex Execute ALUOutput A op B MEM Memory nop WB Write back Register IR 4 0 ALUOutput 13 CS 740 F 00 Load Op Load Ra Mem Rb offset instruction 31 26 ra rb offset 25 21 20 16 15 0 IF Instruction fetch IR IMemory PC PC PC 4 ID Instruction decode register fetch B Register IR 20 16 Ex Execute ALUOutput B SignExtend IR 15 0 MEM Memory Mem Data DMemory ALUOutput WB Write back Register IR 25 21 Mem Data 14 CS 740 F 00 Active Datapath for Load Store Instr 15 0 P C Instr Mem datIn Data Mem Xtnd 25 21 regA 20 16 regB datW datA Reg Array regW 4 IncrPC 25 21 datB Store aluA addr datOut ALU aluB Load Wdest Wdata ALU Operation Used to compute address A input set to extended IR 15 0 ALU function set to add 15 Memory Operation Read for load write for store Write Back To Ra for load None for store CS 740 F 00 Store Store Mem Rb offset Ra instruction Op ra rb offset 31 26 25 21 20 16 15 0 IF Instruction fetch IR IMemory PC PC PC 4 ID Instruction decode register fetch A Register IR 25 21 B Register IR 20 16 Ex Execute ALUOutput B SignExtend IR 15 0 MEM Memory DMemory ALUOutput A WB Write back nop 16 CS 740 F 00 Branch on beq PC Ra 0 PC 4 disp 4 PC 4 equal disp 0x39 ra 31 26 25 21 20 0 IF Instruction fetch IR IMemory PC incrPC PC 4 ID Instruction decode register fetch A Register …
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