Administrivia Class web pages are at http www cs umd edu class spring2009 cmsc411 and d linked li k d iin ffrom CS dept d class l web b pages CMSC 411 Computer Systems y Architecture Lecture 1 Computer Design and Evaluation Class accounts for project will be on CSIC Linux cluster First homework for Unit 1 announced Tuesday 2 3 Start reading Ch Ch 1 of H P Alan Sussman a s cs u d edu als cs umd edu CMSC 411 1 Introduction What can y you expect p to learn Why are you taking this course What to look for in buying a PC brag to parents and friends How computer architecture affects programming style How programming style affect computer architecture How processors disks memory work A great deal of jargon You really y liked the material in 311 and want to learn more The course time fit into your schedule well You needed upper level CS courses and chose this one at random All the courses you really wanted to take were filled CMSC 411 1 3 CMSC 411 1 2 4 Syllabus The Textbook H P Everyone complains about it Virtually y everyone y uses it You can handle it but you have to work at it do the reading Through Th h lecture l t notes t other th references f etc t I ll try to help you put it all together More on web page Importance p of doing g the homework Lecture notes available on the web after class I ll post homework and exam answers after the d date due d t password d protected t t d and d you ll ll gett email with the password account name cmsc411 CMSC 411 1 5 Chapter 1 of H P 6 Early development steps Read Chapter 1 Historical Perspective Section 1 13 Computers as we know them are roughly 60 years old The von Neumann machine model that underlies computer design is only partially von Neumann s Why does Konrad Zuse say he had the the bad luck of being too early early Optional Read his own recollections in TR 180 of ETH Z rich http www inf ethz ch research disstechreps techreports show serial 180 l ang en contains both German and English No one was able to successfully patent the idea of a stored program computer much to the dismay of Eckert and Mauchly CMSC 411 1 CMSC 411 1 Make input and output easier than wiring circuit boards and reading lights Make programming easier by developing higher l level l programming i languages l so that h users did not need to use binary machine code instructions First compilers in late 1950 s for Fortran and Cobol Develop storage devices 7 CMSC 411 1 8 Later development steps Perspective An example Faster More storage g Cheaper Networking and parallel computing Better user interfaces Ubiquitous applications D Development l off standards d d CMSC 411 1 Most powerful computer in 1988 CRAY Y MP 1993 a desktop workstation IBM Power 2 matched its power at less than 10 of the cost How did this happen hardware improvements e g squeezing more circuits into a smaller area improvements in instruction set design e g making the machine faster on a small number of frequently used instructions improvements in compilation e g optimizing code to reduce memory accesses and make use of faster machine instructions 9 CMSC 411 1 10 Crossroads Conventional Wisdom in Comp Arch Old Conventional Wisdom Power is free Transistors expensive New Conventional Wisdom Power wall Power expensive p transistors free Can put more on chip than can afford to turn on Old CW Sufficiently increasing Instruction Level Parallelism ILP via compilers innovation Out of order speculation VLIW New CW ILP wall law of diminishing returns on more HW for ILP Old CW Multiplies are slow Memory access is fast New CW Memory Memory wall wall Memory slow multiplies fast 200 clock cycles to DRAM memory 4 clocks for multiply Old CW Uniprocessor performance 2X 1 5 yrs New CW Power Wall ILP Wall Memory Wall Brick Wall COMPUTER ARCHITECTURE AT A CROSSROADS Uniprocessor performance now 2X 5 yrs Sea change in chip design multiple cores 2X p processors per p chip p 2 years y More simpler processors are more power efficient CMSC 411 1 11 CMSC 411 1 12 Sea Change in Chip Design Crossroads Uniprocessor Performance 10000 From Hennessy and Patterson 4th edition Perfformance vs VA AX 11 780 year Intel 4004 1971 4 bit processor 2312 transistors 0 4 MHz 10 micron PMOS 11 mm2 chip 1000 RISC II 1983 32 bit 5 stage pipeline 40 760 transistors 3 MHz 3 micron NMOS 60 mm2 chip 52 year 100 125 mm2 chip 0 065 micron CMOS 2312 RISC II II FPU Icache Dcache FPU I h D h 10 RISC II shrinks to 0 02 mm2 at 65 nm 25 year Caches via DRAM or 1 transistor SRAM www t ram com Proximity P i it Communication C i ti via i capacitive iti coupling li att 1 TB s TB Ivan Sutherland Sun Berkeley 1 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 VAX 25 year 1978 to 1986 RISC x86 86 52 52 year 1986 tto 2002 RISC x86 year 2002 to present CMSC 411 1 Processor P is i the th new transistor t i t 13 CMSC 411 1 Multiprocessors D j vu all over again Multiprocessors imminent in 1970s 80s 90s today today s s processors are nearing an impasse as technologies approach the speed of light David Mitchell The Transputer The Time Is Now 1989 Transputer was premature Custom multiprocessors strove to lead uniprocessors Procrastination rewarded 2X seq perf 1 5 years We We are dedicating all of our future product development to multicore designs This is a sea change in computing Paul Otellini President Intel 2004 Difference is all microprocessor companies switch to multiprocessors AMD Intel IBM Sun all new Apples 2 CPUs Procrastination penalized 2X sequential perf 5 yrs Biggest programming challenge 1 to 2 CPUs CMSC 411 1 15 14 Problems with Sea Change Algorithms Programming Languages Compilers O Operating ti Systems S t Architectures A hit t Libraries Lib i nott ready to supply Thread Level Parallelism or Data Level Parallelism for 1000 CPUs chip Architectures not ready for 1000 CPUs chip Unlike Instruction Level Parallelism cannot be solved just by computer architects and compiler writers alone but also cannot be solved without participation of computer architects This 4th Edition of textbook Computer Architecture pp explores p shift from A Quantitative Approach Instruction Level Parallelism to Thread Level Parallelism Data Level Parallelism CMSC 411 1 16 Instruction Set Architecture Critical Interface software COMPUTER ARCHITECTURE VS INSTRUCTION SET VS ARCHITECTURE instruction set hardware Properties of a good abstraction 17 CMSC 411 1 0 18 CMSC 411 1 Instruction Set Architecture Example MIPS r0 r1 r31 PC Lasts through many generations portability