ECE/CS 5780/6780: Embedded System DesignScott R. LittleLecture 10: Interrupts in the 6812Scott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 1 / 35General Features of InterruptsAll interrupting systems must have the:Ability for the hardware to request action from the computer.Ability for the computer to determine the interrupt source.Ability for the computer to acknowledge the interrupt.To arm a device means to enable the source of interrupts.To disarm a device means to s hut off the source of interrupts.To enable means to allow interrupts at this time.To disable means to allow postpone interrupts at this time.Scott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 2 / 35Sequence of Events During Interrupt1Hardware needing service makes a busy-to-done transition.2Flag is set in one of the I/O status registers.1Interrupting event sets the flag (ex., TOF=1).2Checks that the device is armed (ex., TOI=1).3Checks that interrupts are enabled (i.e., I=0).3Thread switch.1Microcomputer finishes current instruction (except rev, revw,and wav).2All registers are pushed onto the stack.3Vector address is obtained and put into the PC.4Microcomputer disables interrupts (i.e., sets I=1).4Execution of the ISR.5Return control back to the thread that was running.Scott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 3 / 35Stack Before and After an InterruptScott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 4 / 356812 InterruptsEach interrupt has a 16-bit vector stored in the upper 128 bytesof memory.There are six interrupt sources that are not maskable.1Power-on-reset (POR) or regular hardware RESET pin2Clock monitor reset3COP watchdog reset4Unimplemented instruction trap5Software interrupt instruction (swi)6XIRQ signal (if X bit in CCR = 0)Scott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 5 / 356812 Interrupts (cont)6812 has two external requests IRQ and XIRQ.Other interrupt sources include:10 key wakeup interrupts (Ports J and P)8 input capture/output compare interruptsAn ADC interrupt4 timer interrupts (timer overflow, RTI, 2 pulse accumulators)2 serial port interrupts (SCI and SPI)4 CAN interruptsInterrupts have a fixed priority, but can elevate one to highestpriority using hardware priority interrupt (HPRIO) register.XIRQ is the highest priority interrupt and has separate vectorand enable bit (X).Once X bit is cleared, software cannot disable it.XIRQ handler sets X and I, and restores with rti.Scott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 6 / 356812 Interrupt Vectors and PriorityVector CW# Interrupt Source Enable Arm$FFFE 0 Reset Always Always highest$FFFC 1 COP clk monitor fail Always COPCTL.CME$FFFA 2 COP failure reset Always COP rate selected$FFF8 3 Unimplemented instruction Always Always$FFF6 4 SWI Always Always$FFF4 5 XIRQ X=0 External hardware$FFF2 6 IRQ I=0 INTCR.IRQEN$FFF0 7 Real time interrupt, RTIF I=0 CRGINT.RTIE$FFEE 8 Timer Channel 0, C0F I=0 TIE.C0I$FFEC 9 Timer Channel 1, C1F I=0 TIE.C1I$FFEA 10 Timer Channel 2, C2F I=0 TIE.C2I$FFE8 11 Timer Channel 3, C3F I=0 TIE.C3I$FFE6 12 Timer Channel 4, C4F I=0 TIE.C4I$FFE4 13 Timer Channel 5, C5F I=0 TIE.C5I$FFE2 14 Timer Channel 6, C6F I=0 TIE.C6I$FFE0 15 Timer Channel 7, C7F I=0 TIE.C7I$FFDE 16 Timer overflow, TOF I=0 TIE.TOI$FFDC 17 Pulse acc overflow, PAOVF I=0 PACTL.PAOVI$FFDA 18 Pulse acc input edge, PAIF I=0 PACTL.PAIScott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 7 / 356812 Interrupt Vectors and Priority (cont)Vector CW# Interrupt Source Enable Arm$FFD8 19 SPI complete,SPIF I=0 SPICR1.SPIESPI transmit empty, SPTEF I=0 SPICR1.SPTIE$FFD6 20 SCI transmit buffer empty, TDRE I=0 SCICR2.TIESCI transmit complete, TC I=0 SCICR2.TCIESCI receiver buffer full, RDRF I=0 SCICR2.RIESCI receiver idle, IDLE I=0 SCICR2.ILIE$FFD2 22 ATD sequence complete, ASCIF I=0 ATDCTL2.ASCIE$FFCE 24 Key wakeup J, PIFJ.[7:6] I=0 PIEJ.[7:6]$FFB6 36 CAN wakeup I=0 CANRIER.WUPIE$FFB4 37 CAN errors I=0 CANRIER.CSCIEI=0 CANRIER.OVRIE$FFB2 38 CAN receive I=0 CANRIER.RXFIE$FFB0 39 CAN transmit I=0 CANRIER.TXEIE[2:0]$FF8E 56 Key wakeup P, PIFP.[7:0] I=0 PIEP.[7:0]Scott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 8 / 35External Interrupt Design ApproachIdentify status signal indicating the busy-to-done state transition.Connect the I/O status signal to a microcontroller input thatcan generate interrupts.Scott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 9 / 35Interrupting Software1Ritual - executed once, disable interrupts during, initializeglobals, set port direction, set port interrupt control register,clear interrupt flag, arm device, and enable interrupts.2Main program - initialize SP, execute ritual, interacts with ISRsvia global data (ex. FIFO queue).3ISR(s) - determine interrupt source, implement priority,acknowledge (clear the flag) or disarm, exchange info with mainprogram via globals, execute rti to exit.4Interrupt vectors - in general purpose processors vectors in RAM,in embedded systems usually in ROM.Scott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 10 / 35Setting Interrupt Vectors in Cunsigned short Time;void RTI_Init(void){asm sei // Make atomicRTICTL = 0x73; // 30.517HzCRGINT = 0x80; // ArmTime = 0; // Initializeasm cli}void interrupt 7 RTIHan(void){CRGFLG = 0x80; // AcknowledgeTime++;}Scott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 11 / 35Polled Versus Vectored InterruptsVectored interrupts - each interrupt source has a uniqueinterrupt vector address.Polled interrupts - multiple interrupt sources share the sameinterrupt vector address.Minimal polling - check flag bit that caused interrupt.Polling for 0s and 1s - verify entire status register.Scott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 12 / 35Example of a Vectored InterruptTimeHan movb #$80,TFLG2 ;clear TOF;*Timer interrupt calculations*rtiExtHan movb #$80,PIFJ ;clear flag;*External interrupt calculations*rtiorg $FFDE ;timer overflowfdb TimeHanorg $FFCE ;Key wakeup Jfdb ExtHanScott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 13 / 35Example of a Polled InterruptExtHan brset PIFJ,$80,KJ7Hanbrset PIFJ,$40,KJ6Hanswi ;errorKJ7Han movb #$80,PIFJ ;clear flag0;*KJ7 interrupt calculations*rtiKJ6Han movb #$40,PIFJ ;clear flag1;*KJ6 interrupt calculations*rtiorg $FFCE ;Key wakeup Jfdb ExtHanScott R. Little (Lecture 10: 6812 Interrupts) ECE/CS 5780/6780 14 / 35Keyboard Interface Using InterruptsScott R. Little (Lecture 10: 6812 Interrupts) ECE/CS
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