ECE/CS 5780/6780: Embedded System DesignChris J. MyersLecture 20: Memory InterfacingChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design1 / 41IntroductionMost embedded systems use only the memory built-in to themicrocontroller.Memory interfacing and bus timing is important to understanding internalmicrocontroller architecture.Sometimes internal memory insufficient, and external memory needed.Sometimes external devices are interfaced using memory-mapped I/O.Chris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design2 / 41Memory-Mapped I/OChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design3 / 41Isolated I/OChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design4 / 41Expanded ModeSelect R/W Function0 0 Off0 1 Off1 0 Write1 1 ReadChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design5 / 41Multiplexed Address and Data LinesChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design6 / 41Full-Address DecodingSlave selected only when slave’s address is on the bus.Design using the following steps:1Write specified address using 0,1,X:0100,00XX,XXXX,XXXXfor 1K RAM at $4000-$43FF2Write equation using all 0s and 1s:select =A15· A14· A13· A12· A11· A103Build circuit using gates.Chris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design7 / 41Address Decoder for 1K RAM at $4000-$43FFChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design8 / 41An Address Decoder for I/O Device at $5500Chris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design9 / 41Minimal-Cost Address DecodingUse don’t cares for unspecified addresses to simplify.Example:4K RAM $0000 to $0FFF0000,XXXX,XXXX,XXXXInput $50000101,0000,0000,0000Output $50010101,0000,0000,000116K ROM $C000 to $FFFF11XX,XXXX,XXXX,XXXXChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design10 / 41An Address DecoderChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design11 / 41Karnaugh MapsChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design12 / 41Special CasesSize of the memory is not a power of 2.20K RAM with address range $0000 to $4FFF00XX,XXXX,XXXX,XXXXRange $0000 to $3FFF0100,XXXX,XXXX,XXXXRange $4000 to $4FFFStart address divided by memory size not an integer.32K RAM with address range $2000 to $9FFF001X,XXXX,XXXX,XXXXRange $2000 to $3FFF01XX,XXXX,XXXX,XXXXRange $4000 to $7FFF100X,XXXX,XXXX,XXXXRange $8000 to $9FFFChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design13 / 41Programmable Address DecoderIn Mn An Vn Out0 X X X 01 0 X X 11 1 0 0 11 1 1 0 01 1 0 1 01 1 1 1 1Chris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design14 / 41Timing Intervals(↑ Y, ↓ Y) = (↓ A, ↑ A) + 10(↑ Y, ↓ Y) = (↓ A, ↑ A) + [5, 15](↑ Y, ↓ Y) = (↓ A + [8, 15], ↑ A + [5, 12])Chris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design15 / 41Available and Required Time IntervalsDA = (↓ G∗+ [10, 20], ↑ G∗+ [0, 15])DA = (↓ G∗+ 20, ↑ G∗) worst-caseDR = (↑ Clk −30, ↑ Clk +5)Chris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design16 / 41Timing DiagramsChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design17 / 41Example Timing DiagramsChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design18 / 41Read Cycle CircuitChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design19 / 41Write Cycle CircuitChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design20 / 41Synchronous Bus TimingChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design21 / 41Partially Asynchronous Bus Timing (6809/680x0/x86)Chris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design22 / 41Fully Asynchronous Read CycleChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design23 / 41Fully Asynchronous Write CycleChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design24 / 41Four Types of Control SignalsChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design25 / 41MC9S12C32Chris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design26 / 41MC9S12C32 Modes of OperationBKGD MODB MODA Description Port A Port B MODx write0 0 0 Special In/Out In/Out Write anytime,Single chip not peripheral0 0 1 Emulation A15-A8/ A7-A0 Cannot changeExp. narrow D7-D00 1 0 Special test A15-A8/ A7-A0 Write anytime,Exp. narrow D15-D8 D7-D0 not peripheral0 1 1 Emulation A15-A8/ A7-A0 Cannot changeExp. wide D15-D8 D7-D01 0 0 Normal In/Out In/Out Write once,Single chip Norm exp N/W1 0 1 Normal A15-A8/ A7-A0 Cannot changeExp. narrow D7-D01 1 0 Peripheral − − Cannot change1 1 1 Normal A15-A8/ A7-A0 Cannot changeExp. wide D15-D8 D7-D0Chris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design27 / 41MC9S12C32 Modes of OperationBKGD MODB MODA Description Port A Port B MODx write1 0 0 Normal In/Out In/Out Write once,Single chip Norm exp N/W1 0 1 Normal A15-A8/ A7-A0 Cannot changeExp. narrow D7-D01 1 1 Normal A15-A8/ A7-A0 Cannot changeExp. wide D15-D8 D7-D0Chris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design28 / 41MC9S12C32 Clock CircuitChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design29 / 41MC9S12C32 Expanded Mode Bus TimingChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design30 / 41Address Latch for MC9S12C32Chris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design31 / 41General Approach to Memory InterfacingChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design32 / 41Wide Expanded ModeChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design33 / 418K RAM Read TimingChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design34 / 418K RAM Write TimingChris J. Myers (Lecture 20: Memory Interfacing)ECE/CS 5780/6780: Embedded System Design35 / 418K RAM Write
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