ECE/CS 5780/6780: Embedded System DesignScott R. LittleReview for the Final ExamScott R. Little (Final Exam Review) ECE/CS 5780/6780 1 / 13AdministriviaPlease start lab before you come this week. It WILL take longerthan you think.Lab 10 reports are due BEFORE class on 04/22.6780 students need to schedule a time with me to demo theirfinal projects.The final is 04/30 at 10:30 a.m. in this room.You may want to bring a calculator to the final exam.Scott R. Little (Final Exam Review) ECE/CS 5780/6780 2 / 13Final Exam TopicsMidterm 1 and 2 topics.Motors.Data converters.Memory interfacing and timing diagrams.Hardware verification.Software verification.Scott R. Little (Final Exam Review) ECE/CS 5780/6780 3 / 13MotorsDC motors.Pulse-width modulated control.Stepper motors.Digital control.Used to measure position.Scott R. Little (Final Exam Review) ECE/CS 5780/6780 4 / 13Data convertersDACsR-2R ladder.Precision, range, resolution.ADCsFlash, successive approximation, and dual-slope ADCs.6812 ADC configuration.Scott R. Little (Final Exam Review) ECE/CS 5780/6780 5 / 13Memory interfacing and timing diagramsMemory interfacing.Expanded addressing modes.Address decoding.Timing diagrams.Reading timing diagrams.Scott R. Little (Final Exam Review) ECE/CS 5780/6780 6 / 13Example timing diagram IExample is from the ST M68AW064F data sheet.M68AW064F8/18OPERATIONThe M68AW064F has a Chip Enable power downfeature which invokes an automatic standby modewhenever either Chip Enable is de-asserted(E= High) or LB and UB are de-asserted (LB andUB = High). An Output Enable (G) signal providesa high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/Odata bus. Operational modes are determined bydevice control inputs W, E, LB and UB as summa-rized in the Operating Modes table (see Table 6).Table 6. Operating ModesNote: 1. X = VIH or VIL.Read ModeThe M68AW064F is in the Read mode wheneverWrite Enable (W) is High with Output Enable (G)Low, and Chip Enable (E) is asserted. This pro-vides access to data from eight or sixteen, de-pending on the status of the signal UB and LB, ofthe 1,048,576 locations in the static memory array,specified by the 16 address inputs. Valid data willbe available at the eight or sixteen output pinswithin tAVQV after the last stable address, provid-ing G is Low and E is Low. If Chip Enable or OutputEnable access times are not met, data access willbe measured from the limiting parameter (tELQV,tGLQV or tBLQV) rather than the address. Data outmay be indeterminate at tELQX, tGLQX and tBLQXbut data lines will always be valid at tAVQV.Figure 7. Address Controlled, Read Mode AC WaveformsNote: E = Low, G = Low, W = High, UB = Low and/or LB = Low. Operation E W G LB UB DQ0-DQ7 DQ8-DQ15 PowerDeselected/Power-downVIHXXXX Hi-Z Hi-ZStandby (ISB)Deselected/Power-down X X XVIHVIHHi-Z Hi-ZStandby (ISB)Lower Byte ReadVILVIHVILVILVIHData Output Hi-ZActive (ICC)Lower Byte WriteVILVILXVILVIHData Input Hi-ZActive (ICC)Output DisabledVILXVIHVILX Hi-Z Hi-ZActive (ICC)Output DisabledVILXVIHXVILHi-Z Hi-ZActive (ICC)Upper Byte ReadVILVIHVILVIHVILHi-Z Data OutputActive (ICC)Upper Byte WriteVILVILXVIHVILHi-Z Data InputActive (ICC)Word ReadVILVIHVILVILVILData Output Data OutputActive (ICC)Word WriteVILVILXVILVILData Input Data InputActive (ICC)AI04876tAVAVtAVQV tAXQXA0-A15DQ0-DQ15VALIDDATA VALIDScott R. Little (Final Exam Review) ECE/CS 5780/6780 7 / 13Timing tableM68AW064F10/18Table 7. Read and Standby Mode AC CharacteristicsNote: 1. At any given temperature and voltage condition, tGHQZ is less than tGLQX, tBHQZ is less than tBLQX and tEHQZ is less than tELQX forany given device.2. CL = 5pF.Symbol ParameterM68AW064FUnit55 70Min. Max. Min. Max.tAVAVRead Cycle Time 55 70 nstAVQVAddress Valid to Output Valid 55 70 nstAXQXData hold from address change 10 10 nstBHQZ (1, 2)Upper/Lower Byte Enable High to Output Hi-Z 20 25 nstBLQVUpper/Lower Byte Enable Low to Output Valid 25 35 nstBLQXUpper/Lower Byte Enable Low to Output Transition 5 5 nstEHQZ (1, 2)Chip Enable High to Output Hi-Z 20 25 nstELQVChip Enable Low to Output Valid 55 70 nstELQXChip Enable Low to Output Transition 10 10 nstGHQZ (1, 2)Output Enable High to Output Hi-Z 20 25 nstGLQVOutput Enable Low to Output Valid 25 35 nstGLQXOutput Enable Low to Output Transition 5 5 nstPDChip Enable or UB/LB High to Power Down 55 70 nstPUChip Enable or UB/LB Low to Power Up 0 0 nsScott R. Little (Final Exam Review) ECE/CS 5780/6780 8 / 13Example timing diagram II9/18M68AW064FFigure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.Note: Write Enable (W) = High.Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC WaveformsAI04877tAVAVtAVQV tAXQXtELQVtELQXtEHQZtGLQVtGLQXtGHQZVALIDA0-A15EGDQ0-DQ15VALIDtBLQVtBLQXtBHQZUB, LBAI03856tPDICCtPUISB50%E, UB, LBScott R. Little (Final Exam Review) ECE/CS 5780/6780 9 / 13Timing tableM68AW064F10/18Table 7. Read and Standby Mode AC CharacteristicsNote: 1. At any given temperature and voltage condition, tGHQZ is less than tGLQX, tBHQZ is less than tBLQX and tEHQZ is less than tELQX forany given device.2. CL = 5pF.Symbol ParameterM68AW064FUnit55 70Min. Max. Min. Max.tAVAVRead Cycle Time 55 70 nstAVQVAddress Valid to Output Valid 55 70 nstAXQXData hold from address change 10 10 nstBHQZ (1, 2)Upper/Lower Byte Enable High to Output Hi-Z 20 25 nstBLQVUpper/Lower Byte Enable Low to Output Valid 25 35 nstBLQXUpper/Lower Byte Enable Low to Output Transition 5 5 nstEHQZ (1, 2)Chip Enable High to Output Hi-Z 20 25 nstELQVChip Enable Low to Output Valid 55 70 nstELQXChip Enable Low to Output Transition 10 10 nstGHQZ (1, 2)Output Enable High to Output Hi-Z 20 25 nstGLQVOutput Enable Low to Output Valid 25 35 nstGLQXOutput Enable Low to Output Transition 5 5 nstPDChip Enable or UB/LB High to Power Down 55 70 nstPUChip Enable or UB/LB Low to Power Up 0 0 nsScott R. Little (Final Exam Review) ECE/CS 5780/6780 10 / 13Hardware verificationSimulation.Directed tests.Constrained pseudorandom tests.Coverage MetricsCode coverage metrics.Circuit structure metrics.FSM structure metrics.Functional coverage metrics.Formal methods.Model checkers.Equivalence checkers.Automated theorem proving.Scott R. Little (Final Exam Review) ECE/CS 5780/6780 11 / 13Software verificationUnit testingHarnesses.Stubs.Instrumentation.Regression testing.Coverage metrics.Observability and Controllability.Static analysis.Scott R. Little (Final Exam Review) ECE/CS 5780/6780 12 / 13Other
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