Page 1 1 CS 5780 School of Computing University of Utah CS/ECE 6780/5780 Al Davis Today’s topics: • Serial I/O • general concepts in preparation for Lab 8 2 CS 5780 School of Computing University of Utah Introduction to Serial I/OPage 2 3 CS 5780 School of Computing University of Utah A Serial Channel 4 CS 5780 School of Computing University of Utah DefinitionsPage 3 5 CS 5780 School of Computing University of Utah Bandwidth 6 CS 5780 School of Computing University of Utah More Basics • Classic UART: DTE & DCE communications UART is the port » for Freescale this is SCI (serial communications interface) • this is just one instance • as usual signaling levels are TTL • interface logic can be used to convert to RS232 levels – e.g. MAX232, MC145407 chips » parity is generated by Tx side and checked by Rx sidePage 4 7 CS 5780 School of Computing University of Utah Half Duplex Signalling • Half Duplex normal usage » fixed Tx and Rx side – a.k.a. Simplex signalling expanded version » send can come from either side but only in one direction at a time » problem = collisions • solution same as with Ethernet CDMA • transmit & receive + compare – if Tx & Rx values aren’t the same then collision & retry 8 CS 5780 School of Computing University of Utah Other Issues • Full Duplex more wires but 2 independent communication channels » concurrent send and receive buffers • Timing send and receive baud rates must be the same • Asynchronous (e.g. SCI) separate send and receive clocks » start sequence is used to synch clocks for the frame • model is that drift won’t be enough to cause errors intra-frame • in high speed signaling (e.g. HT, QPI, etc.) – this is a big problem and requires complex and energy hungry circuitry – long transmission paths also require significant pre- and post-emphasis circuits • Synchronous: multiple options common clock (e.g. SPI) Tx side clock – source synchronous signalingPage 5 9 CS 5780 School of Computing University of Utah SCI & SPI Illustrated 10 CS 5780 School of Computing University of Utah Protocols & Specifications • There are many • Each one has specifications electrical » what voltage levels mean what logical value » current sink and source requirements cables » often limited to some max length mechanical » what does the connector look like & pin functionPage 6 11 CS 5780 School of Computing University of Utah 2 Common Freescale Options Simple SCI SCI to RS232 conversion 12 CS 5780 School of Computing University of Utah RS232 Output SpecificationsPage 7 13 CS 5780 School of Computing University of Utah RS232 DB9 Pin Assignments 14 CS 5780 School of Computing University of Utah A Simple Serial NetworkPage 8 15 CS 5780 School of Computing University of Utah RS422/RS423/RS485 Specifications 16 CS 5780 School of Computing University of Utah Universal Serial Bus (USB)Page 9 17 CS 5780 School of Computing University of Utah Optical SCI Channel Where & Why would you want to do this? 18 CS 5780 School of Computing University of Utah SCIPage 10 19 CS 5780 School of Computing University of Utah Transmitting in Asynchronous Mode 20 CS 5780 School of Computing University of Utah Control Bits for the Transmitter NOTE: Tx Data Reg Empty (TDRE) flag signals that the SCDR register is empty, TDRE is cleared by reading it. Different from previous flag clearing methods where you had to write a 1 to the flag. Read of TC flag (transmit complete) similarly clears it Then write to the SCDRPage 11 21 CS 5780 School of Computing University of Utah Transmission Illustrated 22 CS 5780 School of Computing University of Utah Pseudo Code for Transmission ProcessPage 12 23 CS 5780 School of Computing University of Utah Receiving in Asynchronous Mode 24 CS 5780 School of Computing University of Utah Control Bits for the ReceiverPage 13 25 CS 5780 School of Computing University of Utah Status Bits Generated by the Receiver 26 CS 5780 School of Computing University of Utah Receiving IllustratedPage 14 27 CS 5780 School of Computing University of Utah Pseudo Code for Receive Process 28 CS 5780 School of Computing University of Utah 9S12C32 SCI DetailsPage 15 29 CS 5780 School of Computing University of Utah More SCI Details 30 CS 5780 School of Computing University of Utah SCI I/O InterruptsPage 16 31 CS 5780 School of Computing University of Utah SCI Rx, Tx, & ISR’s TxFifo full wait until there is space RxFifo full data was lost due to Rx buffer over run 32 CS 5780 School of Computing University of Utah SCI Interface RitualPage 17 33 CS 5780 School of Computing University of Utah SCI Interface ISR 34 CS 5780 School of Computing University of Utah SCI In/Out CharacterPage 18 35 CS 5780 School of Computing University of Utah Serial Port Printer Interfaces Note: 2 approaches DTR is a handshake saying send me another frame Xoff is a shut up signal – more efficient for larger buffers but some timing complexity for on the fly & response time issues 36 CS 5780 School of Computing University of Utah SCI Simplex Printer Interface (w/ DTR handshake)Page 19 37 CS 5780 School of Computing University of Utah Serial Output w/ DTR 38 CS 5780 School of Computing University of Utah DTR Handshake ISRPage 20 39 CS 5780 School of Computing University of Utah Serial Output to Printer 40 CS 5780 School of Computing University of Utah Using XON/XOFF (busy waiting)Page 21 41 CS 5780 School of Computing University of Utah Synchronous = SPI (3 options) 42 CS 5780 School of Computing University of Utah SPI Master/Slave ExamplePage 22 43 CS 5780 School of Computing University of Utah SPI Fundamentals 44 CS 5780 School of Computing University of Utah More SPI Fundamentals Mode fault occurs when master and slave synchronization is wrong – e.g. 2 mastersPage 23 45 CS 5780 School of Computing University of Utah SPI Pseudo Code 46 CS 5780 School of Computing University of Utah SPI Modes CPOL sets SCLK polarity – e.g. what is IDLE CPHA sets even or odd clock edges for the receiver shift registerPage 24 47 CS 5780 School of Computing University of Utah 9S12C32 SPI Details (Port M) SPIBR register 48 CS 5780 School of Computing University of Utah SPI Control RegistersPage 25 49 CS 5780 School of Computing University of Utah SPI Modes 50 CS 5780 School of Computing University of
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