ECE/CS 5780/6780: Embedded System DesignScott R. LittleLecture 15a: SCI Register Configuration and RitualScott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 1 / 14AdministriviaScheduleThis is the last lecture whose material will be on Midterm 2.3/25 is a midterm review lecture.4/01 is the exam.6780 projects...get started...please!Scott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 2 / 14SCI Register InformationThe information in this lecture is found:Textbook pages 346-9.Chapter 13 of the MC9S12C Family Reference manual(MC9S12C128V1.pdf) which starts at page 383.Scott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 3 / 14SCIBD ConfigurationSCIBD sets the baud rate.SCIBD is a 16 bit register, but only the bottom 13 bits are used.SCI baud rate = Mclk/(16*SCIBD).A value of 26 (decimal) corresponds to a baud rate of 9600 forour MCU.Scott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 4 / 14SCICR1 Configuration IBit 0 - Parity Type (PT)0 - Even parity1 - Odd parityBit 1 - Parity Enable (PE)0 - Disable parity1 - Enable parityBit 2 - Idle Line Type (ILT)0 - Idle character bit count begins after start bit1 - Idle character bit count begins after stop bitBit 3 - Wakeup Condition (WAKE)0 - Idle line (idle condition on RxD) wakeup1 - Address mark (1 in MSB of a received char) wakeupScott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 5 / 14SCICR1 Configuration IIBit 4 - Data Format (M)0 - 1 start bit, 8 data bits, 1 stop bit1 - 1 start bit, 9 data bits, 1 stop bitBit 5 - Receiver Source (RSRC)0 - Internal receiver to transmitter connection1 - External receiver to transmitter connection (via the TxD pin)Bit 6 - SCI Stop in Wait Mode (SCISWAI)0 - SCI enabled in wait mode1 - SCI disabled in wait modeBit 7 - Loop Select (LOOPS)0 - Normal operation1 - Loop operation (SCI received section is disconnected fromthe RxD pin allowing the RxD pin to be used for GPIO.)Scott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 6 / 14SCICR2 Configuration IBit 0 - Send Break (SBK)0 - No break characters1 - Transmit break charactersBit 1 - Receiver Wakeup (RWU)0 - Normal operation1 - Enables wakeup and inhibits receiver interrupts.Bit 2 - Receiver Enable (RE)0 - Disabled1 - EnabledBit 3 - Transmitter E nable (TE)0 - Disabled1 - EnabledScott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 7 / 14SCICR2 Configuration IIBit 4 - Idle Line Interrupt Enable (ILIE)0 - IDLE interrupts disabled1 - IDLE interrupts enabledBit 5 - Receiver Full Interrupt Enable (RIE)0 - RDRF and OR interrupts disabled1 - RDRF and OR interrupts enabledBit 6 - Transmission Complete Interrupt Enable (TCIE)0 - TC interrupts disabled1 - TC interrupts enabledBit 7 - Transmitter I nterrupt Enable (TIE)0 - TDRE interrupts disabled1 - TDRE interrupts enabledScott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 8 / 14SCISR1 Configuration IBit 0 - Parity Error (PF)0 - No parity error1 - Parity errorClear PF by reading SCISR1 followed by SCIDRL. Doesn’t getset in case of OR.Bit 1 - Framing Error (FE)0 - No framing error1 - Framing errorClear FE by reading SCISR1 with FE set followed by SCIDRL.Doesn’t get set in the case of OR. When sets prohibits furtherdata reception.Bit 2 - Noise Flag (NF)0 - No noise1 - NoiseClear NF by reading SCISR! followed by SCIDRL. Doesn’t getset in the case of OR.Scott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 9 / 14SCISR1 Configuration IIBit 3 - Overrun (OR)0 - No overrun1 - OverrunIncoming data is lost, but the current data is intact. Clear ORby reading SCISR1 with OR set followed by SCIDRL.Bit 4 - Idle Line (IDLE)0 - Receiver input is active or has never become active since lastIDLE flag clear1 - Receiver input is idleClear IDLE flag by reading SCISR1 with IDLE set followed bySCIDRL.Bit 5 - Receive Data Register Full (RDRF)0 - Data not available in SCI data register1 - Received data available in SCI data registerClear RDRF by reading SCISR1 with RDRF set followed bySCIDRL.Scott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 10 / 14SCISR1 Configuration IIIBit 6 - Transmit Complete (TC)0 - Transmission in progress1 - No transmission in progressClear TC by reading SCISR1 with TC set then writing toSCIDRL. TC is set when the TDRE flag is set and no data,preamble, or break character is being transmitted.Bit 7 - Transmit Data Register Empty (TDRE)0 - No byte transferred to the transmit shift register1 - Byte transferred to transmit shift registerClear TDRE by reading SCISR1 with TDRE set followed bywriting to SCIDRL.Scott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 11 / 14SCISR2 ConfigurationBit 0 - Receiver Active (RAF)0 - No reception in progress1 - Reception in progressBit 1 - Transmitter Pin Data Direction in Single-Wire Mode(TXDIR)0 - TxD pin used as an input in Single-Wire mode1 - TxD pin used as an output in Single-Wire modeBit 2 - Break Transmit Character Length (BK13)0 - Break character is 10 or 11 bits long1 - Break character is 13 or 14 bits longScott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 12 / 14SCIDRL & SCIDRH ConfigurationSCIDRL is used for bits 0-7 for transmi t and receive.SCIDRH bit 6 is the ninth data bit transmitted when in 9-bitmode.SCIDRH bit 7 is the ninth data bit received when in 9-bit mode.When running in 9-bit mode access SCIDRH before SCIDRL.Scott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 13 / 14SCI RitualScott R. Little (Lecture 15a: SCI Config) ECE/CS 5780/6780 14 /
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