CS/ECE 5780/6780:Embedded System DesignJohn RegehrLecture 16: SCI Register Configuration and RitualSCI Register Information & TerminologyIThe information in this lecture is found:ITextbook pages 346-9.IChapter 13 of the MC9S12C Family Reference manual(MC9S12C128V1.pdf) which starts at page 383.IBreak character: all logic 0s with no start, stop, or parity bits.IIdle character: all logic 1s w ith no start, stop, or parity bits.IPreamble: synchronizing idle character that begins the firsttransmission.SCIBD ConfigurationISCIBD sets the baud rate.ISCIBD is a 16 bit register, but only the bottom 13 bits areused.ISCI baud rate = Mclk/(16*SCIBD).IA value of 26 (decimal) corresponds to a baud rate of 9600 forour MCU.SCICR1 Configuration IIBit 0 - Parity Type (PT)I0 - Even parityI1 - Odd parityIBit 1 - Parity Enable (PE)I0 - Disable parityI1 - Enable parityIBit 2 - Idl e Line Type (ILT)I0 - Idle character bit count begins after start bitI1 - Idle character bit count begins after stop bitIBit 3 - Wakeup Condition (WAKE)I0 - Idle line (idle condition on RxD) wakeupI1 - Address mark (1 in MSB of a received char) wakeupSCICR1 Configuration IIIBit 4 - Data Format (M)I0 - 1 start bit, 8 data bits, 1 stop bitI1 - 1 start bit, 9 data bits, 1 stop bitIBit 5 - Rece iver Source (RSRC)I0 - Internal receiver to transmitter connectionI1 - External receiver to transmitter connection (via the TxDpin)IBit 6 - SCI Stop in Wait Mode (SCISWAI)I0 - SCI enabled in wait modeI1 - SCI disabled in wait modeIBit 7 - Loop Sele ct (LOOPS)I0 - Normal operationI1 - Loop operation (SCI received section is disconnected fromthe RxD pin allowing the RxD pin to be used for GPIO.)SCICR2 Configuration IIBit 0 - Send Break (SBK)I0 - No break charactersI1 - Transmit break charactersIBit 1 - Rece iver Wakeup (RWU)I0 - Normal operationI1 - Enables wakeup and inhibits receiver interrupts.IBit 2 - Rece iver Enable (RE)I0 - DisabledI1 - EnabledIBit 3 - Transmitter Enable (TE)I0 - DisabledI1 - EnabledSCICR2 Configuration IIIBit 4 - Idl e Line Interrupt Enable (ILIE)I0 - IDLE interrupts disabledI1 - IDLE interrupts enabledIBit 5 - Rece iver Full Interrupt Enable (RIE)I0 - RDRF and OR interrupts disabledI1 - RDRF and OR interrupts enabledIBit 6 - Transmission Complete Interrupt Enable (TCIE)I0 - TC interrupts disabledI1 - TC interrupts enabledIBit 7 - Transmitter Interrupt Enable (TIE)I0 - TDRE interrupts disabledI1 - TDRE interrupts enabledSCISR1 Configuration IIBit 0 - Parity Error (PF)I0 - No parity errorI1 - Parity errorIClear PF by reading SCISR1 followed by SCIDRL. Doesn’tget set in case of OR.IBit 1 - Framing Error (FE)I0 - No framing errorI1 - Framing errorIClear FE by reading SCISR1 with FE set followed by SCIDRL.Doesn’t get set in the case of OR. When sets prohibitsfurther data reception.IBit 2 - Noise Flag (NF)I0 - No noiseI1 - NoiseIClear NF by reading SCISR1 followed by SCIDRL. Doesn’tget set in the case of OR.SCISR1 Configuration IIIBit 3 - Overrun (OR)I0 - No overrunI1 - OverrunIIncoming data is lost, but the current data is intact. ClearOR by reading SCISR1 with OR set followed by SCIDRL.IBit 4 - Idl e Line (IDLE)I0 - Receiver input is active or has never become active sincelast IDLE flag clearI1 - Receiver input is idleIClear IDLE flag by reading SCISR1 with IDLE set followed bySCIDRL.IBit 5 - Rece ive Data Register Full (RDRF)I0 - Data not available in SCI data registerI1 - Received data available in SCI data registerIClear RDRF by reading SCISR1 with RDRF set followed bySCIDRL.SCISR1 Configuration IIIIBit 6 - Transmit Complete (TC)I0 - Transmission in progressI1 - No transmission in progressIClear TC by reading SCISR1 with TC set then writing toSCIDRL. TC is set when the TDRE flag is set and no data,preamble, or break character is being transmitted.IBit 7 - Transmit Data Register Empty (TDRE)I0 - No byte transferred to the transmit shift registerI1 - Byte transferred to transmit shift registerIClear TDRE by reading SCISR1 with TDRE set followed bywriting to SCIDRL.SCISR2 ConfigurationIBit 0 - Rece iver Active (RAF)I0 - No reception in progressI1 - Reception in progressIBit 1 - Transmitter Pin Data Direction in Single-Wire Mode(TXDIR)I0 - TxD pin used as an input in Single-Wire modeI1 - TxD pin used as an output in Single-Wire modeIBit 2 - Break Transmit Character Length (BK13)I0 - Break character is 10 or 11 bits longI1 - Break character is 13 or 14 bits longSCIDRL & SCIDRH ConfigurationISCIDRL is used for bits 0-7 for transmit and receive.ISCIDRH bit 6 i s the ninth data bit transmitted when in 9-bitmode.ISCIDRH bit 7 i s the ninth data bit received when in 9-bitmode.IWhen running in 9-bit mode access SCIDRH before SCIDRL.SCI InitializationSCIBD = 26; //9600 baudSCICR1 = 0x00; //no parity, 8 data bits, normal operationSCICR2 = 0x2C; //receiver & transmitter enable,//RDRF interrupt enableSCI Transmit RitualICheck for TDRE by reading SCISR1.IWrite data to SCIDRL.if(SCISR1 & TDRE) {SCIDRL = data;}SCI Receive RitualICheck for RDRF by reading SCISR1.IRead data from SCIDRL.if(SCISR1 & RDRF) {data = SCIDRL;}SCI Initialization#define TDRE 0x80#define RDRF 0x20#define TXINT 0x80void SCI_Init(void){asm seiRxFifo_Init(); // empty FIFOsTxFifo_Init();SCIBD = 52; // 9600 bits/secSCICR1 = 0; // M=0, no paritySCICR2 = 0x2C; // enable, arm RDRFasm cli // enable interrupts}SCI Interface ISR// RDRF set on new receive data// TDRE set on empty transmit registerinterrupt 20 void SciHandler(void){char data;if(SCISR1 & RDRF){RxFifo_Put(SCIDRL); // clears RDRF}if((SCICR2&TXINT)&&(SCISR1&TDRE)){if(TxFifo_Get(&data)){SCIDRL = data; // clears TDRE}else{SCICR2 = 0x2c; // disarm TDRE}}}SCI In/Out Character// Input ASCII character from SCI// spin if RxFifo is emptychar SCI_InChar(void){ char letter;while (RxFifo_Get(&letter) == 0){};return(letter);}// Output ASCII character to SCI// spin if TxFifo is fullvoid SCI_OutChar(char data){while (TxFifo_Put(data) == 0){};SCICR2 = 0xAC; // arm
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