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U of U CS 5780 - Interrupt Synchronization

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ECE/CS 5780/6780: Embedded System DesignScott R. LittleLecture 8: Interrupt SynchronizationScott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 1 / 22AdministriviaMidterm 1 will be on February 14th.Midterm content...Scott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 2 / 22IntroductionInterrupts provide guarantee on response time.Interrupts allow response to rare but important events.Periodic interrupts used for data aquisition and control.Interrupts can provide a way to buffer I/O data.Scott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 3 / 22What are Interrupts?An automatic transfer of software execution i n response tohardware that is asynchronous with current software.Hardware can be external I/O device or internal event.When hardware needs service, it requests an interrupt.Calls interrupt service routine as a background thread.Thread is terminated with rti instruction.Threads may communicate using FIFO queues and synchronizeusing semaphores.Threads share global variables while processes do not.Each potential interrupt has separate arm bit.Interrupt enable bit, I, found in condition code.Scott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 4 / 22Shared versus DedicatedScott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 5 / 22Shared versus DedicatedWire- or negative-logic interrrupt requests:Can add additional I/O devices w/o redesigning H/W.No limit to number of interrupting I/O devices.Microcomputer hardware is simple.Dedicated edge-triggered interrupt requests:Software is simpler, easier to debug, and faster.Less coupling between software modules.Easier to implement priority.Scott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 6 / 22Interrupt Service Routines (ISR)Software executed when hardware requests an interrupt.Polled interrupts - one large ISR handl es all requests.Vectored interrupts - many small, specific ISRs.When the device is armed, the I bit is zero, and an interrupt isrequested, it is serviced as follows:1Execution of main program is suspended.2All registers are pushed onto the stack.3The ISR, or background thread, is executed.4The ISR executes rti instruction.5All registers are restored from the stack.6The main program is resumed.Scott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 7 / 22Interrupt ExecutionScott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 8 / 22When to Use InterruptsGadfly Interrupts DMAPredictable Variable arrival times Low latencySimple I/O Complex I/O High bandwidthFixed load Variable loadSingle thread MultithreadNothing else to do Infrequent alarmsProgram errorsOverflow, illegal opIllegal memory accessMachine/memory errorsPower failureReal-time clocksData acquisition/controlScott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 9 / 22Interthread CommunicationInterrupt threads have logically separate registers/stack, socommunication must occur through global memory.Scott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 10 / 22Input Device InterruptsScott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 11 / 22Output Device InterruptsScott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 12 / 22Other Interrupt IssuesPeriodic interrupts are essential for implementing dataacquisition and control systems.ISR should only occur when needed, come in clean, performfunction, and return right away.Gadfly loops and iterations should be avoided in ISRs.Percent of time in ISRs should be minimized.Interface latency is time between new input available and whensoftware reads the input data.Device latency is response time of external I/O device.A real-time system guarantees a bound on interface latency.Scott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 13 / 22Reentrant ProgrammingA program segment is reentrant if it can be concurrentlyexecuted by two (or more) threads.Reentrant software must place local variables on stack.A nonreentrant subroutine has a section of code called avulnerable window or critical section, and error occurs if:One thread calls a nonreentrant subroutine,A thread is executing in the critical section when interrupted.Second thread calls same sub or shared variable.Mutual exclusion is often implemented by disabling interrupts.Scott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 14 / 22Nonrentrant Subroutine in Cint Result; /* Temporary global variable */int Ave(int x,y){Result = y; /* Save second number */Result = (Result + x) >> 1; /* (1st+2nd)/2 */return(Result);}Scott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 15 / 22Atomic OperationsAtomic operation is one that once started is guaranteed to finish.In most computers, machine instructions are atomic.The following is atomic:inc counter where counter is global variableThe following is nonatomic:ldaa counter where counter is global variableincastaa counterScott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 16 / 22Read-Modify-Write Example1Software reads global variable, producing a copy of the data.2Software modifies the copy.3Software writes modification back into global variable.unsigned int Money; /* bank balance (global) *//* add 100 dollars */void more(void){Money += 100;}Money rmb 2 bank balance implemented as a global* add 100 dollars to the accountmore ldd Money where Money is a global variableaddd #100std Money Money=Money+100rtsScott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 17 / 22Write Followed by Read Example1Software writes to a global variable.2Software reads from global variable expecting original data.int temp; /* global temporary *//* calculate x+2*d */int mac(int x, int d){temp = x+2*d; /* write to a global variable */return (temp);} /* read from global */temp rmb 2 global temporary result* calculate RegX=RegX+2*RegDmac stx temp Save X so that it can be addedlsld RegD=2*RegDaddd temp RegD=RegX+2*RegDxgdx RegX=RegX+2*RegDrtsScott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 18 / 22Nonatomic Multistep Write1Software write part of new value to a global variable.2Software write rest of new value to a global variable.int info[2]; /* 32-bit global */void set(int x, int y){info[0]=x;info[1]=y;}Info rmb 4 32-bit data implemented as a global* set the variable using RegX and RegYset stx Info Info is a 32 bit global variablesty Info+2rtsScott R. Little (Lecture 8: Interrupts) ECE/CS 5780/6780 19 / 22Disabling Interrupts in Cint Empty; /* -1 means empty, 0 means it contains something */int Message; /* data to be communicated */int SEND(int data){ int OK;char SaveSP;asm tpaasm staa SaveSPasm sei


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U of U CS 5780 - Interrupt Synchronization

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