ECE/CS 5780/6780: Embedded System DesignScott R. LittleLecture 21: Analog-to-Digital ConversionScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 1 / 31ADC ParametersPrecision is number of distinguishable ADC inputs.Range is maximum and minimum ADC inputs.Resolution is change in input that causes digital output tochange by 1.Range (volts) = Precision (alternatives) · Resolution (volts)Accuracy usually given for entire instrument (including transducer,analog circuit, ADC, and software).ADC is monotonic if it has no missing codes.ADC is linear if resolution is constant through the range.ADC speed is time to convert.Scott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 2 / 31Common Encoding SchemesUnipolar codes Straight binary Complementary binary+5.00 1111,1111 0000,0000+2.50 1000,0000 0111,1111+0.02 0000,0001 1111,1110+0.00 0000,0000 1111,1111Bipolar codes Offset binary 2s Complement binary+5.00 1111,1111 0111,1111+2.50 1100,0000 0100,0000+0.04 1000,0000 0000,0001+0.00 1000,0000 0000,0000-2.50 0100,0000 1100,0000-5.00 0000,0000 1000,0000Scott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 3 / 31Two-Bit Flash ADCVinX3 X2 X1 Z1 Z02.5 > Vin0 0 0 0 05.0 > Vin≥ 2.5 0 0 1 0 17.5 > Vin≥ 5.0 0 1 1 1 0Vin≥ 7.5 1 1 1 1 1Scott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 4 / 31Successive Approximation ADCScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 5 / 31Sixteen-Bit Dual Slope ADCScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 6 / 31Waveforms During Dual Slope ADC ConversionScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 7 / 31Dual Slope ADC Conversion: TheoryVout(t0)=0tref= t1− t0= 65, 535µsVout(t1)=Vout(t0) −1RC!t1t0Vin(s)ds = −1RCVintrefVout(t2)=0tin= t2− t1Vout(t2)=Vout(t1) −1RC!t2t1Vref(s)ds = Vout(t1) −1RCVreftin=00=−1RCVintref−1RCVreftin0=Vintref+ VreftinVin= −Vreftintref= 10Vtin65, 535µsScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 8 / 31Sigma Delta ADCScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 9 / 31Software Implementation of Sigma Delta ADCunsigned char DOUT; // 8-bit sampleunsigned char SUM; // number of times Z=0 and V0=1unsigned char CNT; // 8-bit countervoid interrupt 13 TOC5handler(void){TFLG1 = OC5; // ack C5FTC5 = TC5+rate; // interrupt 256 times fasterif(Z()) // check inputDACout(0); // too high, set D/A output, V0=0else {DACout(1); // too low, set D/A output, V0=+5vSUM++;}if(++CNT==0){ // end of 256 loops?DOUT = SUM; // new sampleSUM = 0; // get ready for the next}}Scott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 10 / 31ADC InterfaceScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 11 / 31Sample and Hold1Should use polystyrene capacitor because of its high i nsul ationresistance and low dielectric abs orption.2A larger value of C decreases (improves) droop rate. If droopcurrent is IDR, then droop rate is:dVoutdt=IDRC3A smaller C decreases (improves) ac qui sition tim e.Scott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 12 / 31BiFET Analog MultiplexerScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 13 / 31Bilateral SwitchScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 14 / 31Variable-Gain AmplifierScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 15 / 31ADC Block DiagramScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 16 / 31ADC Interrupt Software Without S/HScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 17 / 31ADC Interrupt Software With S/HScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 18 / 31Power and Grounding for the ADC SystemScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 19 / 31Input Protection for CMOS Analog InputsScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 20 / 31Internal ADCs6812 has built-in ADCs with following fe atures:Eight-channel operation.8-bit or 10-bit resolution.Successive approximation conversion technique.Clock and charge pump to create higher voltages.Two operation modes: single sequenc e of conv ersions then stop,and continuous conversion.Supports multiple conversion of single channel, and oneconversion each for group of channels.External VRH, VRLanalog high/low references.Scott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 21 / 316812 ADC System: Setup8 pins of Port AD can be individually configured as analog ordigital inputs using the ATDDIEN register (1 for digital, 0 foranalog).If pin is digital, DDRAD register is used to set pins direction.Can use 8-bit or 10-bit resolution which is selected by setting th eSRES8 bit (1=8-bit) in the ADTCTL4 registerATDCTL2 registe r:ADC system is enabled by setting ADPU to 1.Interrupts are enabled by set ting ASCIE to 1.ASCIF flag is set 1 when conversion sequence is complete, ifASCIE is 1.Scott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 22 / 316812 ADC System: ConversionsWhen ADC is triggered, it performs 1 to 8 conversions.Number of conversions is se lected by the value written into theS8C, S4C, S2C, and S1C bits of ATDCTL3 (values of 0, 8-15are all 8).The channel used is selected by the CC, CB, CA bits ofATDCTL5.All conversions can be on one channel or on multiple channels ifMULT in ATDCTL5 is set (channel sequence determined byS8C, S4C, S2C, S1C).ATDSTAT0 register:SCF flag in ATDSTAT0 is set to 1 when convers ion is complete.CC2, CC1, and CC0 bits are a counter to show conversionprogress.ATDSTAT1 register contains CCFn flag b its for each conversion.Scott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 23 / 316812 ADC System: TriggersConversion can be triggered in three ways:Writing to ATDCTL5 and when done SCF bit in ATDSTAT0 isset.Trigger continuously if SCAN in ATDCTL5 is set.Using an external trigger connected to PAD7.External trigger enabled when ETRIGE bit in ATDCTL2 is set.ETRIGLE ETRIGP External trigger mode0 0 Falling edge of PAD70 1 Rising edge of PAD71 0 Convert while PAD7 is low1 1 Convert while PAD7 is highScott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 24 / 316812 ADC System: Sample PeriodDetermined by ATDCTL4 register and E clock.Sample done in two phases:Phase one transfers sample to ADC’s storage node.Phase two attaches external analog s ignal to the storage no de.SMP1 SMP0 First samp le Second sample Total0 0 2 ADC clocks 2 ADC clocks 4 ADC clocks0 1 2 ADC clocks 4 ADC clocks 6 ADC clocks1 0 2 ADC clocks 8 ADC clocks 10 ADC clocks1 1 2 ADC clocks 16 ADC clocks 18 ADC clocksIf m is 5-bit number formed by PRS4-0 and fEis E clockfrequency:ATD clock frequency =12fE(m + 1)Scott R. Little (Lecture 21: ADCs) ECE/CS 5780/6780 25 / 316812 ADC System: Binary FormatsResults returned in the
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