U of U CS 5780 - Lecture 8 - Interrupt Synchronization

Unformatted text preview:

CS/ECE 5780/6780: Embedded SystemDesignJohn RegehrLecture 8: Interrupt SynchronizationAdministriviaIExam 1 on March 12IntroductionIInterrupts place polling loops into hardware.IInterrupts allow efficien t response to rare but importantevents.IPeriodic interrupts are highly useful for data aquisition andcontrol.IInterrupts can be more predictable than other approaches, orthey can be less predictable , depend ing on how you structurethe system.IInterrupts add concurrency to your embedded software andthis can make your life very d ifficu lt.What are Interrupts?IAn automatic, h ardware-supported transfer of softwareexecution that is asynchronous with respect to currentsoftware.IHardware can be external I/O device or internal event.IWhen hardware needs service, it requests an interrupt.ICalls interrupt service routine (ISR) that you write.IInterrupt is terminated with rti instruction.IInterrupts communicate with main us ing shared memory.IEach potential interrupt has separate arm bit.IInterrupt enable bit, I, found in condition code register.Dedicated vs. SharedDedicated vs. SharedIWire- or negative-logic interrrupt requests:ICan add additional I/O devices w/o redesigning H/W.INo limit to number of interrupting I/O devices.IMicrocomputer hardware is simple.IDedicated edge-triggered interrupt requests:ISoftware is simpler, easier to debug, and faster.ILess coupling between software modules.IEasier to implement priority.Interrupt Service Routines (ISR)ISoftware executed when hardware requests an interrupt.IPolled interrupts - one large ISR handles all requests.IVectored interrupts - many small, specific ISRs.IWhen the device is armed, the I bit is zero, and an interrupt isrequested, it is serviced as follows:1. Execution of main program is suspended.2. All registers are pushed onto the stack.3. The ISR is executed.4. The ISR executes rti instruction.5. All registers are restored from the stack.6. The main program is resumed.Interrupt ExecutionWhen to Use InterruptsGadfly Interrupts DMAPredictable Variable arrival times Low latencySimple I/O Complex I/O High bandwidthFixed load Variable loadNo concurrency Concurrent executionNothing else to d o Infrequent alarmsProgram errorsOverflow, ille gal opIllegal memory accessMachine/memory errorsPower failureReal-time clocksData acquisition/controlCommunication with InterruptsIInterrupts have logically separate registers/stack, socommunication must occur through global mem ory.Input Device InterruptsOutput Device InterruptsOther Interrupt IssuesIPeriodic interrupts are essential for impleme nting dataacquisition and control systems.IISR should only occur when needed, come in clean, performfunction, and return right away.IGadfly loops and iterations shoul d be avoided in ISRs.IPercent of time in ISRs should be minimi zed.IInterface latency is time between new input available andwhen software reads the input data.IDevice latency is response time of external I/O d evice.IA real-time system guarantees bounds on latency of importantoperations.Reentrant ProgrammingIA program segment is reentrant if it can be concurrentlyexecuted by two (or more) interrupts and/or mainIReentrant software must place local variables on stack, or elseuse mutual exclusion.IA nonreentrant s ubroutine has a section of c ode called avulnerable window; an error occurs if:IMain or an interrupt calls a nonreentrant subroutine and isexecuting inside the vulnerable windowIAn interrupt calls same subroutineIMutual exclusion is often implemented by disabling interrupts.Nonrentrant Subroutine in Cint Result; /* Temporary global variable */int Ave(int x,y){Result = y; /* Save second number */Result = (Result + x) >> 1; /* (1st+2nd)/2 */return(Result);}Reentrant or Not?IMust be able to recognize potential sources of bugs due tononreentrant code in high-level languagues.IIs the following atomic?time++;IYes, if the compiler generates:inc timeINo, if the compiler generates:ldd timeaddd #1std timeAtomic OperationsIAtomic operation is one that once started is guaranteed tofinish.IIn most computers, machine instructions are atomic.IThe followin g is atomic:inc counter where counter is global variableIThe followin g is nonatomic:ldaa counter where counter is global variableincastaa counterRead-Modify-Write Example1. Software reads global variable, producing a copy of the data.2. Software modifies the copy.3. Software writes modification back into global variable.unsigned int Money; /* bank balance (global) *//* add 100 dollars */void more(void){Money += 100;}Money rmb 2 bank balance implemented as a global* add 100 dollars to the accountmore ldd Money where Money is a global variableaddd #100std Money Money=Money+100rtsWrite Followed by Read Example1. Software writes to a global variable.2. Software reads from global variable expe cting original data.int temp; /* global temporary *//* calculate x+2*d */int mac(int x, int d){temp = x+2*d; /* write to a global variable */return (temp);} /* read from global */temp rmb 2 global temporary result* calculate RegX=RegX+2*RegDmac stx temp Save X so that it can be addedlsld RegD=2*RegDaddd temp RegD=RegX+2*RegDxgdx RegX=RegX+2*RegDrtsNonatomic Multistep Write1. Software write part of new value to a global variable.2. Software write rest of new value to a global variable.int info[2]; /* 32-bit global */void set(int x, int y){info[0]=x;info[1]=y;}Info rmb 4 32-bit data implemented as a global* set the variable using RegX and RegYset stx Info Info is a 32 bit global variablesty Info+2rtsDisabling Interrupts in Cint Empty; /* -1 means empty, 0 means it contains something */int Message; /* data to be communicated */int SEND(int data){ int OK;char SaveSP;asm tpaasm staa SaveSPasm sei /* make atomic, entering critical */OK=0; /* Assume it is not OK */if(Empty){Message=data;Empty=0; /* signify it is now contains a message*/OK=-1;} /* Successfull */asm ldaa SaveSPasm tap /* end critical section */return(OK);}A Binary Semaphore* Global parameter: Semi4 is the mem loc to test and set* If the location is zero, it will set it (make it -1)* and return Reg CC (Z bit) is 1 for OK* If location is nonzero, return Reg CC (Z bit) = 0Semi4 fcb 0 Semaphore is initially freeTas tst Semi4 check if already setbne Out busy, operation failed, return Z=0dec Semi4 signify it is now busybita #0 operation successful, return Z=1Out rtsInterrupt Synchronization SummaryIWe already talked about h ow device synchronization follows aprotocol that permits the software and hardware


View Full Document

U of U CS 5780 - Lecture 8 - Interrupt Synchronization

Documents in this Course
Lab 1

Lab 1

5 pages

FIFOs

FIFOs

10 pages

FIFOs

FIFOs

5 pages

FIFO’s

FIFO’s

12 pages

MCU Ports

MCU Ports

12 pages

Serial IO

Serial IO

26 pages

Load more
Download Lecture 8 - Interrupt Synchronization
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Lecture 8 - Interrupt Synchronization and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Lecture 8 - Interrupt Synchronization 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?