Lecture 8 EGR 270 Fundamentals of Computer Engineering Reading Assignment Chapter 3 in Logic and Computer Design Fundamentals 4th Edition by Mano Multiplexers Data Selectors A multiplexer MUX is a device that allows several low speed signals to be sent over one high speed output line Select lines are used to specify which input signal is sent to the output A demultiplexer DEMUX performs the opposite task as the multiplexer it divides one high speed input signal into several low speed components Multiplexers and demultiplexers must be synchronized so that the proper signals are selected This type of multiplexing is referred to as time division multiplexing TDM Another type of multiplexing is frequency division multiplexing FDM which is typically covered in a communications course Multiplexed signals are typically transmitted in precisely organized manners according to a set of rules for transmission called a protocol An example of multiplexed signals is shown below using two TTL devices 1 Lecture 8 Several low speed lines EGR 270 Fundamentals of Computer Engineering A B C D 74153 4 x1 MUX 74156 Y Y 1 x4 DeMUX One high speed line S1 S0 Select Lines A B C D Several low speed lines S1 S0 synchronized Select Lines Example Sketch Y for the 4x1 MUX above for A B C D S1 and S0 shown below A B C D S1 S0 Y 2 Lecture 8 EGR 270 Fundamentals of Computer Engineering Multiplexer Design Develop a simple Boolean expressions for a 4x1 multiplexer output Draw the multiplexer circuit 3 Lecture 8 EGR 270 Fundamentals of Computer Engineering Designing multiplexers using decoders and AND OR arrays The previous approach for designing multiplexers results in AND gates with increasing numbers of inputs as the size of the multiplexer increases A better approach based on primitive blocks with reusable code is to construct multiplexers using decoders and AND OR arrays Figure 3 26 4x1 MUX designed using a 2x4 decoder and a 4x2 AND OR array 4 Lecture 8 EGR 270 Fundamentals of Computer Engineering Expanding multiplexers Show how two 4 x 1 multiplexers and a 2 x 1 multiplexer can be used to create an 8 x 1 multiplexer Implementing Boolean functions using multiplexers A multiplexer with N select lines can be used to implement a Boolean function of N 1 variables For example 4x1 MUX 2 two select lines used to implement f A B C 8x1 MUX 3 two select lines used to implement f A B C D 5 16x1 MUX 4 two select lines used to implement f A B C D E Lecture 8 EGR 270 Fundamentals of Computer Engineering General procedure for implementing a function of n variables using a MUX with n 1 select lines 1 List the truth table for the Boolean function 2 The first n 1 variables are applied to the select lines as inputs 3 For each combination of the selection inputs evaluate the output F in terms of a function of the remaining input variable If the variable is X then F will be expresses as 0 1 X or X These values are then applied to the 2 n 1 inputs The circuit generated is illustrated below for functions of 3 or 4 variables I0 I1 I2 0 1 C or C 4x1 MUX Y f A B C 0 1 D or D S1 S0 A B A B C I3 I4 I5 I6 I7 8x1 MUX Y f A B C D S2 S1 S0 6 Lecture 8 EGR 270 Fundamentals of Computer Engineering Example Implement the function f A B C 0 5 6 7 using an 4 x 1 multiplexer 7 Lecture 8 EGR 270 Fundamentals of Computer Engineering Example Implement the function f A B C D A C A B BC D AB CD using an 8 x 1 multiplexer 8 Lecture 8 EGR 270 Fundamentals of Computer Engineering Multiplexer Input Ordering Recall that it is best if the MSB of the function is connected to the MSB of the select lines and so forth If a different order is used beware that the minterms may be in scrambled order Example Consider the two MUX examples below A In the MUX circuit on the left the MSB of the input is connected to the MSB of the select line as recommended Determine the output f A B C B In the MUX circuit on the left inputs A and B have been reversed so care is needed when determining the minterms Determine the output f A B C 0 1 C C 4x1 MUX Y 0 1 C C f A B C S1 S0 4x1 MUX Y f A B C S1 S0 A B B A 9 Lecture 8 EGR 270 Fundamentals of Computer Engineering Other Multiplexer Examples If time allows try the following also covered in the text Implementing a function of 4 variables with a 4x1 MUX rather than an 8x1 MUX Note that using an 8x1 MUX would be more efficient If f A B C D is to be implemented then connect A and B to the select lines A to the most significant select line The inputs for C and D will be one of the following 0 1 C D C D CD CD 10 Lecture 8 EGR 270 Fundamentals of Computer Engineering Demultiplexers and decoders A decoder can also serve as a demultiplexer if the decoder has either Active LOW outputs and an active LOW enable line or Active HIGH outputs and an active HIGH enable line Examples A 4x2 decoder can also serve as a 1x4 DEMUX An 8x3 decoder can also serve as a 1x8 DEMUX A 16x4 decoder can also serve as a 1x16 DEMUX Example Illustrate how the 74155 can be used as a 2x4 decoder or a 1x4 demultiplexer 11 Lecture 8 EGR 270 Fundamentals of Computer Engineering Programmable Logic Devices PLD s See section 6 8 in the text PLD s are used to build customized circuits PLD s contain huge arrays containing hundreds of thousands or perhaps millions of AND OR and NOT gates and flip flops also to be covered in the next chapter PLD s are programmed to make interconnections between the gates thus yielding a single IC that might easily replace huge circuits PLD s are often erasable so that they can be easily reprogrammed PLD s may be mask programmable factory programmed Customized for the user Only feasible in huge quantities Field programmable programmed by the user 12 Lecture 8 EGR 270 Fundamentals of Computer Engineering In order to program a PLD the following items are required PLD there are numerous manufacturers of PLD s They come in various sizes with internal structures that are equivalent to up to hundreds of thousands of equivalent gates VHDL programming software VHDL or VHSIC HDL or Very High Speed Integrated Circuit Hardware Description Language is an IEEE standard language used to implement logic designs HDL s are similar to regular programming languages except that they are specifically oriented to describing hardware structures and behavior Designs may be described structurally similar to a schematic diagram or behaviorally where the software decides …