Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 201Multiplexers (Data Selectors)•A multiplexer (MUX) is a device that allows several low-speed signals to be sent over one high-speed output line.•“Select lines” are used to specify which input signal is sent to the output.•A demultiplexer (DEMUX) performs the opposite task as the multiplexer: it divides one high-speed input signal into several low-speed components.•Multiplexers and demultiplexers must be synchronized so that the proper signals are selected.•This type of multiplexing is referred to as time-division multiplexing (TDM). Another type of multiplexing is frequency-division multiplexing (FDM), which is typically covered in a communications course.•Multiplexed signals are typically transmitted in precisely organized manners according to a set of rules for transmission called a protocol. •An example of multiplexed signals is shown below using two TTL devices.Reading Assignment: Chapter 3 in Logic and Computer Design Fundamentals, 4th Edition by ManoLecture #8 EGR 270 – Fundamentals of Computer Engineering2Example – Sketch Y for the 4x1 MUX above for A, B, C, D, S1, and S0 shown below.A B C D Select Lines 4 x 1 MUX Y (74153) S1 S0 low-speed lines A B C D Select Lines 1 x 4 DeMUX Y (74156) S1 S0 synchronized low-speed lines One high-speed line Several Several S1 D B A C S0 Y Lecture #8 EGR 270 – Fundamentals of Computer Engineering3Multiplexer Design – Develop a simple Boolean expressions for a 4x1 multiplexer output. Draw the multiplexer circuit.Lecture #8 EGR 270 – Fundamentals of Computer Engineering4Designing multiplexers using decoders and AND-OR arrays The previous approach for designing multiplexers results in AND gates with increasing numbers of inputs as the size of the multiplexer increases. A better approach based on primitive blocks with reusable code is to construct multiplexers using decoders and AND-OR arrays.Figure 3-26: 4x1 MUX designed using a 2x4 decoder and a 4x2 AND-OR array.Lecture #8 EGR 270 – Fundamentals of Computer Engineering5Expanding multiplexers – Show how two 4 x 1 multiplexers and a 2 x 1 multiplexer can be used to create an 8 x 1 multiplexer.Implementing Boolean functions using multiplexersA multiplexer with N select lines can be used to implement a Boolean function of (N+1) variables. For example:• 4x1 MUX (2 two select lines) used to implement f(A,B,C)• 8x1 MUX (3 two select lines) used to implement f(A,B,C,D)• 16x1 MUX (4 two select lines) used to implement f(A,B,C,D,E)Lecture #8 EGR 270 – Fundamentals of Computer Engineering6General procedure: (for implementing a function of n variables using a MUX with n-1 select lines):1) List the truth table for the Boolean function.2) The first n-1 variables are applied to the select lines as inputs.3) For each combination of the selection inputs, evaluate the output F in terms of a function of the remaining input variable. If the variable is X, then F will be expresses as 0, 1, X, or X’. These values are then applied to the 2n-1 inputs.The circuit generated is illustrated below for functions of 3 or 4 variables.8 x 1MUXYS1 S0AB0, 1, D, or D’f(A, B, C, D)I0I1I2I3I4I5I6I7 S2Cf(A,B,C)4 x 1MUXYS1 S0B A 0, 1, C, or C’Lecture #8 EGR 270 – Fundamentals of Computer Engineering7Example: Implement the function f(A, B, C) = (0, 5, 6, 7) using an 4 x 1 multiplexer.Lecture #8 EGR 270 – Fundamentals of Computer Engineering8Example: Implement the function f(A, B, C, D) = A’C’ + A’B + BC’D’ + AB’CD’ using an 8 x 1 multiplexer.Lecture #8 EGR 270 – Fundamentals of Computer Engineering9Multiplexer Input Ordering:Recall that it is best if the MSB of the function is connected to the MSB of the select lines (and so forth). If a different order is used, beware that the minterms may be in scrambled order. Example: Consider the two MUX examples below:A)In the MUX circuit on the left, the MSB of the input is connected to the MSB of the select line as recommended. Determine the output, f(A,B,C).B)In the MUX circuit on the left, inputs A and B have been reversed so care is needed when determining the minterms. Determine the output, f(A,B,C).Lecture #8 EGR 270 – Fundamentals of Computer Engineeringf(A,B,C) = ( ?)4 x 1MUXYS1 S0BA 0 1CC’f(A,B,C) = ( ?)4 x 1MUXYS1 S0AB 0 1CC’10Other Multiplexer Examples:If time allows, try the following (also covered in the text)•Implementing a function of 4 variables with a 4x1 MUX (rather than an 8x1 MUX).•Note that using an 8x1 MUX would be more efficient.•If f(A,B,C,D) is to be implemented, then connect A and B to the select lines (A to the most significant select line). The inputs for C and D will be one of the following: 0, 1, C’D’, C’D, CD’, CD)Lecture #8 EGR 270 – Fundamentals of Computer Engineering11Demultiplexers and decodersA decoder can also serve as a demultiplexer if the decoder has either:• Active-LOW outputs and an active-LOW enable line or• Active-HIGH outputs and an active-HIGH enable lineExamples:A 4x2 decoder can also serve as a 1x4 DEMUXAn 8x3 decoder can also serve as a 1x8 DEMUXA 16x4 decoder can also serve as a 1x16 DEMUXExample: Illustrate how the 74155 can be used as a 2x4 decoder or a 1x4 demultiplexer.Lecture #8 EGR 270 – Fundamentals of Computer Engineering12Programmable Logic Devices (PLD’s) – See section 6.8 in the textPLD’s are used to build customized circuits. PLD’s contain huge arrays containing hundreds of thousands (or perhaps millions) of AND, OR, and NOT gates (and flip-flops also – to be covered in the next chapter). PLD’s are programmed to make interconnections between the gates, thus yielding a single IC that might easily replace huge circuits. PLD’s are often erasable so that they can be easily reprogrammed.PLD’s may be:mask programmable – factory programmed. Customized for the user. Only feasible in huge quantities.Field programmable – programmed by the user.Lecture #8 EGR 270 – Fundamentals of Computer Engineering13In order to program a PLD, the following items are required:-PLD – there are numerous manufacturers of PLD’s. They come in various sizes with internal structures that are equivalent to up to hundreds of thousands of equivalent gates.-VHDL programming software