ELE22MIC Aug 2004 Microprocessors 68HC11 Instruction Set Reference Page 1 ELE22MIC Aug 2004 Microprocessors 68HC11 Instruction Set Reference Page 2 ELE22MIC Aug 2004 Microprocessors 68HC11 Instruction Set Reference Page 3 ELE22MIC Aug 2004 Microprocessors 68HC11 Instruction Set Reference Page 4 ELE22MIC Aug 2004 Microprocessors 68HC11 Instruction Set Reference Page 5 ELE22MIC Aug 2004 Microprocessors 68HC11 Instruction Set Reference Page 6 68HC11 Instruction Set by Instruction Category ARITHMETIC ADDITION ABA ABX ABY ADCA ADCB ADDA ADDB ADDD A A B IX IX B IY IY B A A M CarryFlag B B M CarryFlag A A M B B M D D M SUBTRACTION SBA A A B SBCA A A M CarryFlag SBCB B B M CarryFlag SUBA A A M SUBB B B M SUBD D D M TWOS COMPLEMENT NEGATE NEG M M NEGA A A BEGB B B M M 1 A A 1 B B 1 SP SP 1 IX IX 1 INCREMENT INC INCA INCB INS INX INY M M 1 A A 1 B B 1 SP SP 1 IX IX 1 IY IY 1 D A B DIVIDE IDIV FDIV IX D IX D D IX IX D IX D D IX FDIV treats args as fractions ARITHMETIC SHIFT LEFT Multiply by 2 ASL Arithmetic Shift Left M ASLA Arithmetic Shift Left A ASLB Arithmetic Shift Left B ASLD Arithmetic Shift Left D RIGHT Divide By 2 ASR Arithmetic Shift Right M ASRA Arithmetic Shift Right A ASRB Arithmetic Shift Right B LOGICAL SHIFT ELE22MIC Aug 2004 Logical Shift Left M Logical Shift Left A Logical Shift Left B Logical Shift Left D SHIFT RIGHT LSR Logical Shift Right M LSRA Logical Shift Right A LSRB Logical Shift Right B LSRD Logical Shift Right D ROTATE LEFT used to extend multiply ROL ROtate Left M ROLA ROtate Left A ROLB ROtate Left B RIGHT used to extend divide ROR ROtate Right M RORA ROtate Right A RORB ROtate Right B BINARY CODED DECIMAL BCD DAA Decimal Adjust after Addition DECREMENT DEC DECA DECB DES DEX MULTIPLY MUL LEFT LSL LSLA LSLB LSLD Branch Jump BRA Branch Always BRN Branch Never JMP JSR Jump to Address Jump to Subroutine NOP No OPeration i e do nothing but fetch next instruction CLEAR bit s 0 SET bit s 1 CLR M 0 CLRA A 0 CLRB B 0 BCLR Clear Bits M BSET Set Bits M COMPARE TEST CONDITION CODE MANIPULATION CLC CarryFlag 0 Clear Carry Flag CLV OVerflowFlag 0 Clear Overflow Flag SEC CarryFlag 1 Set Carry Flag SEV OVerflowFlag 1Set Overflow Flag TAP CCR A Transfer A to Condition Codes Register CCR TPA A CCR Transfer CCR to A CONDITIONAL Branches BEQ Branch if EQual BNE Branch if Not Equal BCC Branch if CarryFlag is Clear Microprocessors 68HC11 Instruction Set Reference Page 7 BCS Branch if CarryFlag is Set BRCLR Branch if bits clear BRSET Branch if bits set Conditional Branches using SIGNED NUMERIC INTERPRETATION BMI Branch if MInus BPL Branch if PLus BVS Branch if oVerflow Set BVC Branch if oVerflow Clear BLT Branch if Less Than BGE Branch if Greater Than or Equal to BLE Branch if Less Than or Equal to Branches for UN SIGNED NUMERIC INTERPRETATION BHI Branch if HIgher than BHS Branch if Higher or Same BLS Branch if Lower or Same BLO Branch if Lower DATA MOVEMENT Push Push register value onto stack PSHA M SP A PSHB M SP B PSHX M SP IX LOW M SP IX HIGH PSHY M SP IY LOW M SP IY HIGH XGDX D IX XGDY D IY INTERRUPT HANDLING CLI Clear interrupt Mask SEI Set interrupt Mask SWI Software Interrupt RTI Return from Interrupt WAI Wait for interrupt LOGICAL LOGICAL AND ANDA A A M ANDB B B M LOGICAL EXCLUSIVE OR EORA A A M EORB B B M LOGICAL OR ORAA A A M ORAB B B M ONES COMPLEMENT NOT COM M M COMA A A COMB B B MISCELLANEOUS STOP Stop clocks TEST Special test mode Pull Pull POP value from stack to Register PULA A M Sp PULB B M SP PULX X HIGH M SP X LOW M SP PULY Y HIGH M SP Y LOW M SP Load Register LDAA A M LDAB B M LDD D M LDS SP M LDX X M LDY Y M Store Register STAA STAB STD STX STY A M B M D M M 1 M A M 1 B IX M M 1 IY M M 1 Transfer Registers TAB A B TBA B A TSX IX SP 1 TSY IY SP 1 TXS SP IX 1 TXY SP IY 1 Exchange Registers ELE22MIC Aug 2004 Microprocessors 68HC11 Instruction Set Reference Page 8 ELE22MIC Aug 2004 Microprocessors 68HC11 Instruction Set Reference Page 9