ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 1ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 2ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 3ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 4ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 5ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 6ELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 768HC11 Instruction Set by Instruction CategoryARITHMETIC ADDITIONABA A = A + BABX IX = IX + BABY IY = IY + BADCA A = A + M + CarryFlagADCB B = B + M + CarryFlagADDA A = A + MADDB B = B + MADDD D = D + MSUBTRACTIONSBA A = A - BSBCA A = A - M - CarryFlagSBCB B = B - M - CarryFlagSUBA A = A - MSUBB B = B - MSUBD D = D - MTWOS COMPLEMENT (NEGATE)NEG M = -MNEGA A = -ABEGB B = -BDECREMENTDEC M = M - 1DECA A = A - 1DECB B = B - 1DES SP = SP - 1DEX IX = IX - 1INCREMENTINC M = M + 1INCA A = A + 1INCB B = B + 1INS SP = SP + 1INX IX = IX + 1INY IY = IY + 1MULTIPLYMUL D = A * BDIVIDEIDIV IX = D / IX, D = D % IXFDIV IX = D / IX, D = D % IX (FDIV treats args as fractions)ARITHMETIC SHIFT LEFT: (Multiply by 2)ASL Arithmetic Shift Left (M)ASLA Arithmetic Shift Left (A)ASLB Arithmetic Shift Left (B)ASLD Arithmetic Shift Left (D) RIGHT: (Divide By 2)ASR Arithmetic Shift Right (M)ASRA Arithmetic Shift Right (A)ASRB Arithmetic Shift Right (B)LOGICAL SHIFT LEFT:LSL Logical Shift Left (M)LSLA Logical Shift Left (A)LSLB Logical Shift Left (B)LSLD Logical Shift Left (D) SHIFT RIGHT: LSR Logical Shift Right (M)LSRA Logical Shift Right (A)LSRB Logical Shift Right (B)LSRD Logical Shift Right (D)ROTATE LEFT: (used to extend multiply)ROL ROtate Left (M)ROLA ROtate Left (A)ROLB ROtate Left (B) RIGHT: (used to extend divide)ROR ROtate Right (M)RORA ROtate Right (A)RORB ROtate Right (B)BINARY CODED DECIMAL (BCD) DAA Decimal Adjust after AdditionBranch & JumpBRA Branch AlwaysBRN Branch NeverJMP Jump to AddressJSR Jump to SubroutineNOP No OPeration ; i.e do nothing but fetchnext instructionCLEAR (bit(s) = 0) & SET (bit(s) = 1)CLR M = 0CLRA A = 0CLRB B = 0BCLR Clear Bits (M)BSET Set Bits (M)COMPARE & TESTCONDITION CODE MANIPULATIONCLC CarryFlag = 0 Clear Carry FlagCLV OVerflowFlag = 0 Clear Overflow FlagSEC CarryFlag = 1 Set Carry FlagSEV OVerflowFlag = 1Set Overflow FlagTAP CCR = A Transfer A toCondition CodesRegister (CCR)TPA A = CCR Transfer CCR to ACONDITIONAL BranchesBEQ Branch if EQualBNE Branch if Not EqualBCC Branch if CarryFlag is ClearELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page 8BCS Branch if CarryFlag is SetBRCLR Branch if bits clearBRSET Branch if bits set Conditional Branches using SIGNED NUMERICINTERPRETATIONBMI Branch if MInusBPL Branch if PLusBVS Branch if oVerflow SetBVC Branch if oVerflow ClearBLT Branch if Less ThanBGE Branch if Greater-Than or Equal-toBLE Branch if Less-Than or Equal-to Branches for UN-SIGNED NUMERICINTERPRETATIONBHI Branch if HIgher thanBHS Branch if Higher or SameBLS Branch if Lower or SameBLO Branch if LowerDATA MOVEMENT Push - Push register value onto stackPSHA M[SP--] = A PSHB M[SP--] = BPSHX M[SP--] = IX.LOW ; M[SP--] = IX.HIGHPSHY M[SP--] = IY.LOW ; M[SP--] = IY.HIGH Pull - Pull (POP) value from stack to Register PULA A = M[++Sp] PULB B = M[++SP]PULX X.HIGH = M[++SP] ; X.LOW =M[++SP]PULY Y.HIGH = M[++SP] ; Y.LOW =M[++SP] Load RegisterLDAA A = MLDAB B = MLDD D = MLDS SP = MLDX X = MLDY Y = M Store RegisterSTAA A -> MSTAB B -> MSTD D -> M:M+1([M] = A, [M+1] = B)STX IX -> M:M+1STY IY -> M:M+1 Transfer RegistersTAB A = BTBA B = ATSX IX = SP + 1TSY IY = SP + 1TXS SP = IX - 1TXY SP = IY - 1 Exchange RegistersXGDX D <=> IXXGDY D <=> IYINTERRUPT HANDLING:CLI ; Clear interrupt MaskSEI ; Set interrupt MaskSWI ; Software InterruptRTI ; Return from InterruptWAI ; Wait for interruptLOGICALLOGICAL ANDANDA A = A & MANDB B = B & MLOGICAL EXCLUSIVE OREORA A = A ^ MEORB B = B ^ MLOGICAL ORORAA A = A | MORAB B = B | MONES COMPLEMENT (NOT)COM M = M#COMA A = A#COMB B = B#MISCELLANEOUSSTOP Stop clocksTEST Special test modeELE22MIC Microprocessors Aug 2004 68HC11 Instruction Set Reference Page