1 EGR 270 Fundamentals of Computer Engineering File: N270L4 Lab # 4 Decoders and Multiplexers Lab Format - This is a Individual Lab so each student must design and test their own circuits. - Students are free to assist each other in all labs. - Each student must complete the Preliminary Work Section before lab begins. Preliminary Work will be checked in lab and will be part of the lab report grade. - Each student must submit his or her own lab report. - Lab reports will not be accepted until all required circuits have been demonstrated to the instructor. A. Objective The objective of this laboratory is to investigate the design and use of decoders and multiplexers. Boolean functions will be implemented using both decoders and multiplexers. B. Materials Breadboard 5V Power Supply Wire, switches, etc. 74LS151 8 x 1 Data Selector (multiplexer) 74LS155 Dual 2 x 4 Decoder/Demultiplexer 74LS04 Hex Inverter 74LS08 Quad 2-input AND C. Introduction Decoders A decoder is a combinational logic circuit that activates one of several output lines based on the input code (typically binary or BCD). Shown below in Figure 1 is a block diagram and a truth table for a 2-line-to-4-line (or 2 x 4) decoder that has active-HIGH inputs and outputs. 2 x 4Decoder(MSB) ABD0D1D2D30Inputs OutputsA B D0 D1 D2 D301101011000010000100001Figure 1: 2 x 4 decoder with active-HIGH inputs and outputs2 Note that functionally the outputs of the decoder above correspond to minterms. So, Active-HIGH decoder outputs are equivalent to minterms For example, BA = m = D00- (for 2 inputs) or D0 = m = A B C D0- - - (for 4 inputs) A combinational logic function that is expressed as a sum of minterms, therefore, can be implemented by summing decoder outputs, or F = ∑(minterms) = ∑(active-HIGH decoder outputs) For example, if f(A,B) = (0, 2, 3) then f (A,B)= D0 + D2 + D3 so f can be implemented by the circuit shown in Figure 2. 2 x 4Decoder(MSB) ABD0D1D2D3Figure 2: f(A,B) = f(A,B)(0,2,3) implement using a 2 x 4 decoder Some decoders, such as the 74155, have active-LOW outputs. Figure 3 shows a block diagram and a truth table for a 2 x 4 decoder with active-LOW outputs. 2 x 4Decoder(MSB) ABD0D1D2D30Inputs OutputsA B D0 D1 D2 D301101010111101111011110Figure 3: 2 x 4 decoder with active-LOW inputs and outputs Note that functionally the outputs of the decoder above correspond to maxterms. So, Active-LOW decoder outputs are equivalent to maxterms For example, D0 = m = M = A B C D = (A + B + C + D)0 0- - -. A combinational logic function that is expressed as a product of maxterms, therefore, can be implemented by ANDing decoder outputs, or F = ∏(maxterms) = ∏(active-LOW decoder outputs) For example, if f(A,B) = (0, 1, 3) then f (A,B)= D0 - D1 - D3 so f can be implemented by the circuit shown in Figure 4. 2 x 4Decoder(MSB) ABD0D1D2D3Figure 4: f(A,B) = f(A,B)(0,1,3) implement using a 2 x 4 decoder3 Multiplexers A multiplexer, or data selector, can be also be used to implement combinational logic circuits. A multiplexer implementation table is used to determine the input connections for the multiplexer. A 2 x 1 multiplexer can be used to implement a function of 2 variables, such as f(A,B) A 4 x 1 multiplexer can be used to implement a function of 3 variables, such as f(A,B,C) A 8 x 1 multiplexer can be used to implement a function of 4 variables, such as f(A,B,C,D) Procedure: 1) Draw the truth table 2) Determine which inputs will be connected to the select lines (note which is the MSB) 3) Express the output F in terms of the other input. 4) Draw the MUX logic diagram. Example: Implement the function f(A,B,C) = (0, 3, 6, 7) using a 4 x 1 multiplexer. The multiplexer implementation table is shown below in Figure 5. A B C F 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 Figure 5: MUX implementation table The circuit can be implemented as shown in Figure 6. Keep in mind in the example above that bits A and B were connected to the select lines. If any other bits are connected to the select lines, then the implementation table needs to be rearranged. I0 I1 I2 I3 S1 S0 F(A,B,C) = (0,3,6,7) C 0 1 (MSB) A B Y 4x1 MUX Figure 6: F(A,B,C) = (0,3,6,7) implemented using a 4x1 multiplexer F = C’ (so connect C’ to MUX input 0) F = C F = 1 F = 0 Connect A and B to select lines Express F in terms of the other input (C) MUX Input 04 D. Preliminary Work Include instructions with each step. 1. 3x8 Decoder Circuit: Function f(A,B,C) is defined as follows: f(A,B,C) = (1st 4 unique digits in your Student ID that are less than 8). If you do not have 4 digits that are less than 8, then add in as many of the following digits as are necessary: 7, 2, 6, 4. For example, if your Student ID is 1468413, then f(A,B,C) = (1,3,4,6). Express f(A,B,C) as a sum of minterms and as a product of maxterms (shorthand notation). 2. Logic Diagram for 3x8 decoder circuit using PSPICE. Use PSPICE to generate a logic diagram that uses a 74155 3x8 decoder to implement the product of maxterms expression from the previous step. The logic diagram should include: - Display sssigned chip numbers and part numbers (For example: U1 – 74LS08) - If multiple gates are used, use as many as possible from a given IC (for example, use U1A, U1B, U1C, etc., rather than U1A, U2A, U3A, etc.) - Input switches (including DIP switches, resistors, etc) - Label all inputs and outputs. Label input A as the MSB. - Output LED, including current-limiting resistor - Include text on the schematic page with information such as your name, course number, lab number, and the function to be implemented. - Extra credit (5 points): Simulate the PSPICE circuit above. Produce a second schematic for the simulation as you will need replace the dip switches with Digital Clocks. The output LED and current limiting resistor are also unnecessary. Be sure to use use the part LO is a 0 input is needed. The analog 0 ground cannot be used. 3. Modified Logic Diagram for 3x8 decoder circuit using the 74156. The 74156 is similar to the 74155 except that it has open-collector outputs. Since open-collector outputs allow for wire-ANDing, repeat step 2 using a 74156 (don't forget the pull-up resistor). 4. 8x1 Multiplexer Circuit. Design a multiplexer circuit using the 74151 to implement the function f(A,B,C,D) = (1st 4 unique digits in your