1 EGR 270 Fundamentals of Computer Engineering File: N270L3 Lab #3 Combinational Logic Circuits and 7-Segment Displays Lab Format - This is a Individual Lab so each student must design and test their own circuits. - Students are free to assist each other in all labs. - Each student must complete the Preliminary Work Section before lab begins. Preliminary Work will be checked in lab and will be part of the lab report grade. - Each student must submit his or her own lab report. - Lab reports will not be accepted until all required circuits have been demonstrated to the instructor. A. Objective The objective of this laboratory is to investigate the design procedure for combinational logic circuits discussed in class and to use the design procedure to design and build a custom combinational logic circuit. Some commonly used combinational logic functions are already available commercially and do not have to be designed from scratch. An example is a BCD-to-7-segment decoder. In this lab a 7-segment display will be driven using a commercially available BCD-to-7-segment decoders. B. Materials Breadboard 5V Power Supply Wire, switches, resistors, etc. Common-anode 7-segment display (GNS-3011, LDS3221, MAN72A, or other) 74LS47 BCD-to-7-segment decoder/driver (common anode) 74LS00, 74LS02, 74LS04, 74LS08, 74LS32, and 74LS86 IC’s C. Introduction Combinational logic circuits can be divided into two categories: 1) Custom circuits - Unique circuits where there is no commercially available device. In this case the design procedure for combinational logic circuits can be used. 2) Commercially available devices - Including decoders, encoders, multiplexers, BCD-to-7-segment decoders, magnitude comparators, etc. Note that the general design procedure could be used to design these devices, but it is unnecessary and the commercial devices are often optimized for reduced delay. Design Procedure (for combinational logic circuits) 1. Specification: Write a specification for the circuit if one is not provided. 2. Formulation: Derive the truth table or initial Boolean equations that define the required relationships between inputs and outputs. 3. Optimization: Apply two-level and multiple-level optimization using Karnaugh Maps or Boolean algebra. Draw a logic diagram or provide a netlist using AND, OR, and NOT gates. 4. Technology Mapping: Implement the circuit using the desired technology, such as using AND/OR/NOT gates, decoders, multiplexters, PLDs, FPGA, etc. 5. Verification: Verify the correctness of the circuit (perhaps by hand analysis or computer simulation). Example: See examples of the design procedure in the class notes.2 BCD-to-7-segment decoders Since BCD-to-7-segment decoders are commercially available, we don’t need to design them using the design procedure. Recall from class notes that there are two types of BCD-to-7-segment decoders: a) Common-cathode decoder - Uses active-HIGH outputs (i.e., a HIGH output is used to light a segment) - Must be used with a common-cathode 7-segment display - Example: 74LS48 - See Figure 1 below b) Common-anode decoder - Uses active-LOW outputs (i.e., a LOW output is used to light a segment) - Must be used with a common-anode 7-segment display (such as the GNS-3011 or LDS-3221) - Example: 74LS47 (we will use this type in lab) - See Figure 2 below Figure 1: 7448 and a common-cathode 7-segment display Figure 2: 7447 and a common-anode 7-segment display D C B A (LSB) D C B A (LSB)3 D. Preliminary Work (Include instructions with each step in your report). 1. 7-segment display and decoder circuit. A. Generate a logic diagram using PSPICE for Circuit 1 including: - 7-segment display (check with the instructor to see which part will be used in lab). o If the MAN72A or LDS3221 is to used in lab, the following part can be used in PSPICE since it has the same pinout: LDS-A30R (in the Discrete Library). Note that the Discrete Library is not part of the evaluation version, so you can’t analyze circuits with this component. o If the GNS-3011 is to be used in lab, the following part can be used in PSPICE since it has the same pinout: LDS-A32R (in the Discrete Library). - 7447 BCD-to-7-segment decoder (or the 7446 if it is not available, since it has the same pinout) - Input switches (DIP switches, resistors, etc). Be sure to label the switches (A,B,C,D). - No PSPICE simulation is required (simply draw the schematic) - Add text to the schematic (name, course, lab number, title of circuit, etc) Circuit 1: Testing the 7447 and a common-anode 7-segment display B. Check the data sheet for the 7447 (see course website) to determine the function of LT, BI / RBO, RBI. Write out a clear description of each (in your own words). C. Show how to connect four 7447 IC’s (using a simple block diagram) such that leading zeros will not be displayed (for example, the displays will show (blank)607 rather than 0607). D. Check the data sheet for the 7447 to determine the pattern that is lit on the 7-segment display for each of the 16 possible inputs. Illustrate the results with sketches (or copy them from the data sheet). (continued on next page) D C B A (LSB) Dip Switches4 2. Student ID Conversion Circuit. Use the design process to design a combinational logic circuit that will convert the digits 0-6 to the 7 digits in your student ID. It should also convert the digit 7 to a 9. For example, if your student ID is 1302477 then the circuit should make the following conversions: 0  1 1  3 2  0 3  2 4  4 5  7 6  7 7  9 In particular, include the following: A) List the numbers to be converted using your Student ID (similar to the boxed section above). B) Draw a truth table. Note that there should be 3 inputs and 4 outputs. C) Form minimal SOP and POS expression using Kmaps. D) If the circuit is to be implemented using any of the following types of logic gates, determine the fewest number of gates possible. Consider SOP, POS, gate sharing, XORs, etc. 7400 – 2-input NAND 7404 – NOT 7402 – 2-input NOR 7408 – 2-input AND 7432 – 2-input OR 7486 – 2-input XOR E) Generate a Logic Diagram using PSPICE for Circuit 2A including: - Show assigned chip numbers and part numbers (For example: U1 – 7447). - Be sure to use all available gates on a given IC before using another IC of the same