PowerPoint PresentationSlide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 121Reading Assignment: Chapter 3 in Logic and Computer Design Fundamentals 4th Edition by Mano Lecture #6 EGR 270 – Fundamentals of Computer EngineeringIn Chapters 1-2 we concentrated on analyzing or minimizing given truth tables or logic diagrams.In Chapter 3 we concentrate more on designing logic circuits to accomplish a given task.Chapter 3 introduces a general design procedure that can be used to design combinational logic circuits. We will also look at commercially-available logic circuits.2Lecture #6 EGR 270 – Fundamentals of Computer EngineeringDesign Procedure (for combinational logic circuits)1. Specification: Write a specification for the circuit if one is not provided.2. Formulation: Derive the truth table or initial Boolean equations that define the required relationships between inputs and outputs.3. Optimization: Apply two-level and multiple-level optimization. Use Boolean algebra, Karnaugh maps, or other techniques to optimize the circuit. Draw a logic diagram using AND, OR, and NOT gates or provide a netlist (software).4. Technology Mapping: Transform the logic diagram or netlist to a new diagram or netlist using the available implementation technology. Options might include:•Implement with AND-OR-NOT gates•Implement with Exclusive-OR gates and other basic logic gates•Implement with only NANDs or only NORs•Implement using decoders•Implement using multiplexers•Implement using PLDs or FPGAs (programmable devices)5. Verification: Verify the correctness of the circuit using methods such as:•Hand analysis•PSPICE simulation•VHDL simulation•Build in lab and test the circuit3Example: Design a 4-bit prime number indicator where the output P = 1 when the binary value of the input ABCD represents a prime number.Lecture #6 EGR 270 – Fundamentals of Computer Engineering4Example: Design a 4-bit magnitude comparator, where the output M = 1 when the inputs A3A2A1A0 and B3B2B1B0 are equal.Lecture #6 EGR 270 – Fundamentals of Computer Engineering5Example: Design a code converter to convert a BCD code to an Excess-3 code. Treat all invalid inputs as don’t cares.Lecture #6 EGR 270 – Fundamentals of Computer Engineering6BCD-to-7-segment decoder/driverThis is a special type of decoder that is used to drive a 7-segment display.There are two types of 7-segment displays using LED’s:1) common anode (all anodes at +5V)2) common cathode (all cathodes at ground)If a common-cathode display is used (as shown below) and if the decoder outputs a HIGH on output a, then segment a will be lit. Note that “current-limiting resistors” are required for each segment or else the segment may be destroyed due to excessive current. The 7448 is a commercially available BCD-to-7-segment decoder/driver with active-HIGH outputs so it is intended to drive a common-cathode display.a b c d e f g (MSB) A B a b c d Figure 6: BCD to 7-segment decoder e f g C D (with active-HIGH and outputs) a b c d e f g Common-cathode 7-segment display 7448 a anode cathode Typical segment Lecture #6 EGR 270 – Fundamentals of Computer Engineering7Similarly, a common-anode display requires a driver with active-LOW outputs, such as the 7447.a b c d e f g (MSB) A B a b c d Figure 7: BCD to 7-segment decoder e f g C D (with active-LOW outputs) a b c d e f g Common-anode 7-segment display 7447 a cathode anode Typical segment +5V Figure 3-12 below illustrates which segments would typically be lit for each of the BCD inputs. Note that the unused inputs (10-15) could be handled in a variety of ways:1)Blank display2)Display unique patterns not equal to any of the decimal digits3)Treat as don’t cares for simplest circuit.Lecture #6 EGR 270 – Fundamentals of Computer Engineering8Example: Design a BCD-to-7-segment decoder to drive a common anode display with a blank display for all illegal inputs.Lecture #6 EGR 270 – Fundamentals of Computer Engineering9Technology MappingIf an initial design is specified using AND, OR, and NOT gates, the design may thenbe converted (or mapped) into a new technology. Examples in the text include:1) Mapping a design to NAND logic2) Mapping a design to NOR logicNote that NAND and NOR gates are “universal gates”, meaning that they can be usedto form any other type of basic logic gates. Figure 3-14 on the following pageillustrates the mapping of other gates into NAND and NOR gates.Show how to form other logic gates using NANDs:Lecture #6 EGR 270 – Fundamentals of Computer Engineering10Figure 3-6: Mapping of AND gates, OR gates, and Inverters to NAND gates, NOR gates, and Inverters.Lecture #6 EGR 270 – Fundamentals of Computer Engineering11Procedure for converting (mapping) a circuit into NAND or NOR circuits:1. Replace each AND and OR gate with the NAND (NOR) gate and inverter equivalent circuits.2. Cancel all inverter pairs (back-to-back inverters).3. Without changing the logic function, “push” all inverters through branches to represent them as multiple inverters. Example: Implement the following optimized function with NAND gates and inverters.F = AB + (AB)’C + (AB)’D’ + ELecture #6 EGR 270 – Fundamentals of Computer Engineering12Example: Repeat the last example using NOR gates and inverters.F = AB + (AB)’C + (AB)’D’ + ELecture #6 EGR 270 – Fundamentals of Computer