PowerPoint PresentationSlide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 141Recall that three methods for designing sequential circuits will be covered:1) Excitation table method (already covered)2) State equation method3) “One-Hot” methodDesigning Sequential Circuits using State EquationsBefore the state equation method is covered, two related topics must be covered:• state equations• flip-flop characteristic equationsState EquationsA state equation is an equation for the next state of a sequential logic circuit. It has the form:Q(t + 1) = (Boolean expression involving present states and inputs) The state equations are simply formed using the “Next State” shown in the state table.Reading Assignment: - Chapter 5 in Logic and Computer Design Fundamentals, 4th Edition by ManoLecture #14 EGR 270 – Fundamentals of Computer Engineering2Example: Find the state equations for the state diagram shown below.001234001001111Lecture #14 EGR 270 – Fundamentals of Computer Engineering3Flip-flop characteristic equationsFlip-flop behavior has been expressed so far using truth tables or excitation tables. The next state (output) of a flip-flop can also be described algebraically using a flip-flop state equation or flip-flop characteristic equation.Example: Develop the flip-flop characteristic equation for a JK flip-flop.Lecture #14 EGR 270 – Fundamentals of Computer Engineering4Example: Develop flip-flop characteristic equations for SR, D, and T flip-flops.Lecture #14 EGR 270 – Fundamentals of Computer Engineering5Designing Sequential Circuits using State Equations – Procedure1. Form the state table.2. Develop the state equations from the state table.3. Determine the type of flip-flop to be used.4. Manipulate the state equation into the form of the characteristic equation for each flip-flop. This will yield the flip-flop input expressions.Notes:•It is easiest to design by state equations using D flip-flops.•Many PLD’s only support D flip-flop designs, so state equations are very useful.•JK flip-flop designs will yield the simplest circuits in general.•Designing circuits by the excitation table method and by the state equation method should yield the same results.Lecture #14 EGR 270 – Fundamentals of Computer Engineering6Example: Design a modulo-7 counter by the state equation method using:A) D flip-flopsLecture #14 EGR 270 – Fundamentals of Computer Engineering7Example: Design a modulo-7 counter by the state equation method using:B) JK flip-flops.Lecture #14 EGR 270 – Fundamentals of Computer Engineering8Three methods for designing synchronous sequential circuits:1) Excitation table method (already covered)2) State equation method (already covered)3) “One-Hot” method“One-Hot” Method for designing synchronous sequential circuitsThe “one-hot” method is based on the idea that N flip-flops will be used to represent N states and that at any given time only one of the states is “hot” or HIGH – the current state.Example: A state diagram with 4 states would require 4 flip-flops and the outputs would be as follows:Q 1Q 0Q 0Q 0Other connections and circuitryState A is “hot”Q 0Q 1Q 0Q 0Other connections and circuitryState B is “hot”(Similar diagrams for states C and D are not shown.)Lecture #14 EGR 270 – Fundamentals of Computer Engineering9“One-Hot” Method - Advantage The design process is simple for the “one-hot” method. The connections for D flip-flop designs can be seen easily from an ASM (Algorithmic State Machine) Chart, which is similar to a flowchart. Also note that this method can allow for a simple way to describe sequential circuits in VHDL.Algorithmic State Machine (ASM) Chart symbolsASM Charts are covered in more detail in Chapter 8 of the text. For now, we will just introduce two ASM chart symbols (elements).State 0EntryExit1-bit Condition10Exit 1Exit 0EntryState boxDecision boxLecture #14 EGR 270 – Fundamentals of Computer Engineering10“One-Hot” Method - DisadvantageThe “one-hot method requires a potentially large number of flip-flops. Since the states are not encoded as with other methods (i.e., one flip-flop is required for each state), designs may require a large number of flip-flops. Examples are provided below to illustrate this problem.Sequential Circuit# flip-flops using encoded states (state equations or excitation table method).# flip-flops = log2(# states)# flip-flops using the “one-hot” method.# flip-flops = # states3-bit (mod-8) counter3 88-bit counter 8 256Circuit with 20 states5 20Note: When we implement sequential circuits using Aldec Active-HDL into specific PLDs, the software gives us a choice of implementing a “one-hot” design (the default) or using encoded states (which saves many flip-flops).Lecture #14 EGR 270 – Fundamentals of Computer Engineering11Example: Use the “one-hot” method to design a mod-5 counter. Note that each state box essentially acts like a D flip-flop where the entry to the box is D and the exit from the box is Q.01234State diagramState 0State 1State 2State 3State 4ASM ChartSo Q0(t+1) = D0 = Q4So Q1(t+1) = D1 = Q0So Q2(t+1) = D2 = Q1So Q3(t+1) = D3 = Q2So Q4(t+1) = D4 = Q3Lecture #14 EGR 270 – Fundamentals of Computer Engineering12Example (mod-5 counter continued): Q0(t+1) = D0 = Q4Q1(t+1) = D1 = Q0Q2(t+1) = D2 = Q1Q3(t+1) = D3 = Q2Q4(t+1) = D4 = Q3D0 Q0Q0D1 Q1Q1D2 Q2Q2D3 Q3Q3D4 Q4Q4CKLogic DiagramA) Label the output on the logic diagram above for state 4 (count 4)B) Redraw the logic diagram with an encoder added to encode the statesLecture #14 EGR 270 – Fundamentals of Computer Engineering13Example: Use the “one-hot” method to design a mod-5 counter UP/DOWN.Let x be an input control where if:• x = 0 the counter counts down• x = 1 the counter counts up01234State diagram0000011111ASM Chart:State 0State 1x = 0 or 1?10State 2x = 0 or 1?10State 3x = 0 or 1?10State 4x = 0 or 1?10x = 0 or 1?10Q0(t+1) = D0 =Q1(t+1) = D1 =Q2(t+1) = D2 =Q3(t+1) = D3 =Q4(t+1) = D4 =Find the state equations:Lecture #14 EGR 27014Example (mod-5 UP/DOWN counter continued) : Draw the logic diagramLecture #14 EGR 270 – Fundamentals of Computer