EGR 270 Fundamentals of Computer Engineering Filename Aldec9 1Ex1 Combinational Logic Circuits using Aldec Active HDL 9 2 and Xilinx ISE 14 2 Aldec Active HDL software can be used to generate and simulate designs using VHDL Aldec is not targeted to any one specific manufacturer of programmable logic devices PLDs or Field Programmable Gate Arrays FPGAs but produces a vhd file that can be implemented or synthesized into various devices using various synthesis tools We will use Xilinx ISE WebPack 14 to synthesize our design into the Xilinx Spartan 3E FPGA This FPGA is conveniently mounted on an FPGA board called by BASYS2 by Digilent The BASYS2 provides easy access to input and output pins slide switches and pushbutton switches for inputs LEDs and 7segment displays for outputs USB2 video and PS2 ports and PMOD connectors for interfacing with other devices Aldec Active HDL Define inputs and outputs Describe functional operation Create testbench and test design Generate truth tables and waveforms Compile and produce vhd file vhd file e g MyFile vhd Xilinx ISE Specify FPGA Package Xilinx Spartan 3E etc Assign signals to pins Implement design Generate reports Produce bit file bit file e g MyFile bit Digilent Adept Program to download bit files into Digilent devices Identify FPGA board BASYS2 Identify bit file Download Program the FPGA USB2 cable 1 Digilent BASYS2 FPGA Board This tutorial will guide you through Using Aldec Active HDL software to o Enter and compileVHDL code for a simple combinational logic circuit o Generate a testbench and simulate the design o Produce truth tables and waveforms verifying proper operation Using Xilinx ISE software to o Specify the type of FPGA to be programmed o Assign input and output signals to FPGA pins o Implement the design producing a bit file o Generate reports Using Digilent Adept software to o Select the board to be programmed Digilent BASYS2 FPGA board o Select the bit file to be used o Program the FPGA board Testing the design on the BASYS2 board 1 Creating a Project with Aldec Active HDL Launch Aldec Active HDL 9 2 The screen below should appear Select Next 2 Select Create new workspace as shown below and then select OK Enter a name for the workspace Ex1 was entered below change the location of the workspace folder or use the default as below and select OK Note that the name for the project workspace VHDL entity to be entered later and architecture to be entered later should be the same Use letters numbers and underscores only for filenames 3 Select Create an Empty Design with Design Flow as shown below and select Next The next window that appears shows information about synthesis tools and implementation tools that might be configured to launch automatically from Aldec Active HDL Synthesis tools can also be launched separately rather than integrating them into Aldec We will launch Xilinx ISE separately so you can ignore most settings shown Select VHDL for the Default HDL Language and then select Next 4 Enter the design name Note that it should match the workspace name used earlier Ex1 for this example Enter the name and select Next Select Finish on the final screen shown below 2 Adding VHDL code to your design Before adding VHDL code to the design recall that VHDL designs typically have three parts o Entity basically defines the inputs and outputs to a black box o Architecture defines the function of the black box o Testbench defines stimulus signals as inputs to the design and allows us to observe the outputs typically in the form of truth tables or timing diagrams The diagram below illustrates the relationship between the entity architecture and testbench 5 The Design Flow Manager screen should appear next The Design Browser should appear on the left of the screen If it does not appear it can be toggled on and off using Alt 1 Double click on Add New File under the Design Browser and the Add New File window should appear Note that there are several types of files that can be specified VHDL Source Code Block Diagram etc Additionally some wizards are available to allow for easier entry of design information Select the Wizards tab under Add New File After selecting the Wizards tab select VHDL Source Code and then select OK 6 The VHDL Source File Wizard is used to specify the inputs and outputs that will be used in the entity and architecture sections of the VHDL file to be created Ex1 vhd If the function to be implemented is F A B C D 0 1 4 5 7 8 10 14 A C A BD ACD B C D then we will need 4 inputs A B C D and one output F Select Next when the screen below on the left appears Enter the source file name Ex1 in the window shown below on the right and select Next Select New in the window below on the left to add a new port Name it A with direction in Also add input ports B C and D and output port F as shown below and then select Finish The diagram should clearly illustrate your inputs and outputs 7 Note that a VHDL file Ex1 vhd has now been generated with a complete entity section and the shell of the architecture section Only the architecture description Boolean equation for F in this example needs to be entered Note that the entity portion of the VHDL files was completed by the wizard Enter architecture description here The VHDL file is complete after entering the architecture description as shown below Completed architecture description 8 Select the Compile button to compile the design If there were any errors correct them and recompile the design Compile button Successfully compiled 9 3 Simulating VHDL Code We have already defined the entity and the architecture for the design Now we need to define the testbench to simulate the design to see if it works correctly Selecting the following option will make later printing of truth tables and waveforms easier Select Tools Preferences and the Preferences window below should appear as shown below Select Waveform Viewer Editor and change the default waveform viewer editor to Standard Waveform Viewer Editor and then select Apply and then OK To generate a testbench for your design go to the Tools menu and select Generate Testbench as shown below 10 Select the entity name and the architecture name in the window shown below on the left and then select Next Also select Next in the window shown below on the right Select Next in the window below on the left and Finish in the window below on the right 11 Change the Design Browser so that ex1 ex1 is displayed and expand the TestBench folder click on the