Lecture 20 EGR 270 Fundamentals of Computer Engineering Reading Assignment Section 2 10 in Logic and Computer Design Fundamentals 4th Edition by Mano Three State Devices Tri State Devices Devices used so far have two output states logic 0 or logic 1 Tri state devices have three output states 1 Logic 0 2 Logic 1 3 High impedance Z state When a tri state device is in the high Z state the output appears to be disconnected This allows several outputs to be connected together such as in the case where several outputs are connected to a common bus Although tri state outputs are available with various types of gates the most common is probably the tri state buffer Input A Output Y A if C 1 High Z if C 0 Control C Tri state buffer 1 Lecture 20 EGR 270 Fundamentals of Computer Engineering 2 Lecture 20 EGR 270 Fundamentals of Computer Engineering Octal 3 state buffer 3 Reference John Wakerly Digital Design Principles Practices 3rd Edition Prentice Hall Lecture 20 EGR 270 Fundamentals of Computer Engineering Application Connecting several peripheral devices to a bus Can be used to indicate when certain counts occur Similarly they can be used to start or stop events at certain times Note in the example below that the bus controller connects Device 2 to the bus and Devices 1 and 3 are in the high Z state 4 bit bus Z Z Z Z 0 0 1 1 Device 1 0 1 0 Bus Controller 1 0 0 1 1 0 0 1 Z Z Z Z 1 0 0 1 1 1 0 0 Device 2 Device 3 4 Lecture 20 EGR 270 Fundamentals of Computer Engineering Rather than show each wire in a bus it is more convenient to show a bus as follows 8 Notation for an 8 bit bus The last diagram repeated using bus notation 4 1 Z 4 Z 4 0 Device 1 1 4 0 Bus Controller Device 2 Device 3 5 Lecture 20 EGR 270 Fundamentals of Computer Engineering Application Using two 74541 IC s to connect two 8 bit user inputs to a common data bus DB connected to a microprocessor 6 Reference John Wakerly Digital Design Principles Practices 3rd Edition Prentice Hall Lecture 20 EGR 270 Fundamentals of Computer Engineering Transceiver A device capable of transferring information in either direction A transceiver can be constructed using two tri state buffers along with some control logic as shown below A B Enable Direction Enable 0 enable transceiver 1 disable transceiver Direction 0 transfer A to B 1 transfer B to A Buffer Control Lines 1 enable buffer 0 disable buffer high Z 7 Lecture 20 EGR 270 Fundamentals of Computer Engineering Illustration Add logic values to the diagrams below to illustrate the transceiver operation A Case 1 Enable 1 B Enable Direction A Case 2 Enable 0 Direction 0 Enable Direction A Case 3 Enable 0 Direction 1 B B Enable Direction 8 Lecture 20 EGR 270 Fundamentals of Computer Engineering Octal 3 state transceiver 9 Reference John Wakerly Digital Design Principles Practices 3rd Edition Prentice Hall Lecture 20 EGR 270 Fundamentals of Computer Engineering Application Octal 3 state transceiver used to connect two data buses Figure 5 60 Bidirectional buses and transceiver operation 10 Reference John Wakerly Digital Design Principles Practices 3rd Edition Prentice Hall Lecture 20 EGR 270 Fundamentals of Computer Engineering Tri state outputs with PLD s Recall that the GAL22V10 PLD was discussed earlier It has 22 Output Logic MacroCells OLMCs that can be configured as inputs or outputs How is this possible By using tri state buffers 11