Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 111Reading Assignment: Section 2.10 in Logic and Computer Design Fundamentals, 4th Edition by ManoThree-State Devices (Tri-State Devices)Devices used so far have two output states: logic 0 or logic 1Tri-state devices have three output states:1) Logic 02) Logic 13) High impedance (Z) state When a tri-state device is in the high Z state, the output appears to be disconnected. This allows several outputs to be connected together, such as in the case where several outputs are connected to a common bus. Although tri-state outputs are available with various types of gates, the most common is probably the tri-state buffer.A if C = 1High Z if C = 0Tri-state bufferOutput Y = Input AControl CLecture #20 EGR 270 – Fundamentals of Computer Engineering2Lecture #20 EGR 270 – Fundamentals of Computer Engineering3Octal 3-state buffer:Reference: John Wakerly, Digital Design – Principles & Practices, 3rd Edition, Prentice-HallLecture #20 EGR 270 – Fundamentals of Computer Engineering4Application: Connecting several peripheral devices to a bus Can be used to indicate when certain counts occur. Similarly, they can be used to start or stop events at certain times.Note in the example below that the bus controller connects Device 2 to the bus and Devices 1 and 3 are in the high-Z state.4-bit busDevice 1BusControllerDevice 2 Device 3 0 1 0 Z Z Z Z Z Z Z Z 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 01001Lecture #20 EGR 270 – Fundamentals of Computer Engineering5Rather than show each wire in a bus, it is more convenient to show a bus as follows:Device 1BusControllerDevice 2 Device 3 0 1 0 Z Z 18Notation for an 8-bit busThe last diagram repeated using bus notation:444 4Lecture #20 EGR 270 – Fundamentals of Computer Engineering6Application: Using two 74541 IC’s to connect two 8-bit user inputs to a common data bus (DB) connected to a microprocessorReference: John Wakerly, Digital Design – Principles & Practices, 3rd Edition, Prentice-HallLecture #20 EGR 270 – Fundamentals of Computer Engineering7Transceiver - A device capable of transferring information in either direction. A transceiver can be constructed using two tri-state buffers along with some control logic, as shown below.ABEnableDirectionEnable0: enable transceiver1: disable transceiverDirection0: transfer A to B1: transfer B to ABuffer Control Lines1: enable buffer0: disable buffer (high Z)Lecture #20 EGR 270 – Fundamentals of Computer Engineering8Illustration – Add logic values to the diagrams below to illustrate the transceiver operation.ABEnableDirectionABEnableDirectionABEnableDirectionCase 1: Enable = 1Case 2: Enable = 0Direction = 0Case 3: Enable = 0Direction = 1Lecture #20 EGR 270 – Fundamentals of Computer Engineering9Octal 3-state transceiver:Reference: John Wakerly, Digital Design – Principles & Practices, 3rd Edition, Prentice-HallLecture #20 EGR 270 – Fundamentals of Computer Engineering10Application: Octal 3-state transceiver used to connecttwo data buses:Reference: John Wakerly, Digital Design – Principles & Practices, 3rd Edition, Prentice-HallFigure 5-60Bidirectional busesand transceiveroperation.Lecture #20 EGR 270 – Fundamentals of Computer Engineering11Tri-state outputs with PLD’s:Recall that the GAL22V10 PLD was discussed earlier. It has 22 Output Logic MacroCells (OLMCs) that can be configured as inputs or outputs. How is this possible? By using tri-state buffers.Lecture #20 EGR 270 – Fundamentals of Computer