1 EGR 270 Fundamentals of Computer Engineering File: N270L7 Lab # 7 Sequential Circuit Design using FPGAs Lab Format • This is a Individual Lab so each student must design and test their own circuits. • Each student must complete the Preliminary Work Section before lab begins. Preliminary Work will be checked in lab and will be part of the lab report grade. • Each student must submit his or her own lab report. • Lab reports will not be accepted until all required circuits have been demonstrated to the instructor. A. Objective The objective of this laboratory is to introduce students to the use of sequential circuit design using Field Programmable Gate Arrays (FPGAs). Each student will design a sequential circuit using the State Diagram Wizard in Aldec Active HDL. The design will be simulated in Aldec Active HDL and the corresponding VHDL file will be combined with other VHDL files to provide for a 1Hz clock input and an output display on a 7-segment display. The complete design will be synthesized using Xilinx ISE 11 and implemented into a Spartan 3E FPGA on the BASYS2 FPGA board where the student can test the design for proper operations. B. Materials Aldec Active-HDL Software Xilinx ISE 11 Software Digilent Adept Software BASYS2 FPGA Board C. Reference Refer to the following items (available on the course Bb site): • “Sequential Logic Circuits using Aldec Active-HDL 8.1 and Xilinx ISE 11” • “Combinational Logic Circuits using Aldec Active-HDL 8.1 and Xilinx ISE 11” • Digilent BASYS2 FPGA Board Reference Manual D. Introduction Although we will make use of the State Diagram Wizard in Aldec Active-HDL, we could also enter a design for a sequential circuit directly in VHDL. One method for doing this is to write state equations. In order to give the student an appreciation of the design work that would be required by hand and the complexity of the circuit to be implemented into the FPGA, students will be required to perform a hand design as well. Sequential circuit design using state equations Several design methods are available for designing synchronous sequential circuits, including the excitation table method, design by state equations, and design using the “one-hot” method. Since the D flip-flop is an essential part of the FPGA, we will focus on the state equation method which is well suited for D flip-flops. The general form of the state equation for a D flip-flop is: So the input for each D flip-flop is simply determined by finding an expression for the next state for that flip-flop. Q(t + 1) = D2 Example: Design a 4-bit counter using D flip-flops and the state equation method. A 4-bit counter, also called a modulo-16 counter, counts in the sequence 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 and repeats. The state diagram is shown in Figure 1 below. 0 4 12 8 1 2 1315 3 14 9 1011 5 6 7Figure 1: State diagram for a 4-bit counter The corresponding state table is shown in Figure 2 below. Note that the state is shown in decimal form in the state diagram, whereas it is shown in binary form in the state table with bit D as the MSB. Present State Next State D C B A D C B A 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 Figure 2: State table for a 4-bit counter3 The characteristic equation for a D flip-flop is very simple: Q(t + 1) = D. So the expression for the next state is simply connected to the D input on the flip-flop. Expressions for the next state for each of the four flip-flops is determined using Karnaugh maps shown in Figure 3 below. 0 0 0 00 0 1 01 1 0 11 1 1 1DCBA 00 01 11 10000111100 0 1 01 1 0 11 1 0 10 0 1 0DCBA 00 01 11 100001111001 0 10 1 0 10 1 0 10 1 0 1DCBA 00 01 11 10000111101 0 0 11 0 0 11 0 0 11 0 0 1DCBA 00 01 11 1000011110D(t + 1) C(t + 1) B(t + 1) A(t + 1)Figure 3: Karnaugh maps for the state equations for the 4-bit counter Minimal SOP expressions for each output yield the state equations shown below in Figure 4: D(t + 1) = D C + D B + D A + D C B AC(t + 1) = CB + C A + C B AB(t + 1) = BA + BAA(t + 1) = A• • • • • ••• •••• Figure 4: State equations for the 4-bit counter The state equations above are implemented in the circuit shown below in Figure 5. DD QD QDClockD (MSB)CBCount DC QC QC DD QB QBA DA QA QA ABCD(DCBA)D(t + 1)C(t + 1)B(t + 1)A(t + 1)DCDBDADCBACBCACBABABAA Figure 5: Logic Diagram for the 4-bit counter E. Preliminary Work4 1. Draw the state diagram for the custom counter described below: Each student should design an up/down counter that will count out each of the unique digits (7 or below) of his or her EmplID in the order in which they occur, followed by the all digits from 0 to 7 that do not occur in the EmplID from highest to lowest. Note that all counting sequences will have all eight digits. The counter should include a count direction control, X, such that the counter will count in the manner described above when X = 1 and in reverse order when X = 0. An example is shown below. Example: EmplID = 1468443 Counting sequence when X = 1: 1, 4, 6, 3, 7, 5, 2, 0 Counting sequence when X = 0: 0, 2, 5, 7, 3, 6, 4, 1 (i.e., reverse order) 2. Design the custom counter described above using D flip-flops and the state equation method. Include the state table and Karnaugh maps used to determine the D flip-flop inputs. Draw the final circuit (similar to the one shown for the example in Figure 5). Assume that gates with any number of inputs are available. What is the total number of gates required (including the 3 flip-flops)? F. Laboratory Work 1. Ask the instructor to check your state diagram before proceeding to specify the design using the Aldec Active-HDL software. 2. Use the State Diagram Wizard using Aldec Active HDL to draw your state diagram, including all required inputs and outputs …