EGR 270 Fundamentals of Computer Engineering File N270L7 Lab 7 Sequential Circuit Design using FPGAs Lab Format A This is a Individual Lab so each student must design and test their own circuits Each student must complete the Preliminary Work Section before lab begins Preliminary Work will be checked in lab and will be part of the lab report grade Each student must submit his or her own lab report Lab reports will not be accepted until all required circuits have been demonstrated to the instructor Objective The objective of this laboratory is to introduce students to the use of sequential circuit design using Field Programmable Gate Arrays FPGAs Each student will design a sequential circuit using the State Diagram Wizard in Aldec Active HDL The design will be simulated in Aldec Active HDL and the corresponding VHDL file will be combined with other VHDL files to provide for a 1Hz clock input and an output display on a 7 segment display The complete design will be synthesized using Xilinx ISE 11 and implemented into a Spartan 3E FPGA on the BASYS2 FPGA board where the student can test the design for proper operations B Materials Aldec Active HDL Software Xilinx ISE 11 Software Digilent Adept Software BASYS2 FPGA Board C Reference Refer to the following items available on the course Bb site Sequential Logic Circuits using Aldec Active HDL 8 1 and Xilinx ISE 11 Combinational Logic Circuits using Aldec Active HDL 8 1 and Xilinx ISE 11 Digilent BASYS2 FPGA Board Reference Manual D Introduction Although we will make use of the State Diagram Wizard in Aldec Active HDL we could also enter a design for a sequential circuit directly in VHDL One method for doing this is to write state equations In order to give the student an appreciation of the design work that would be required by hand and the complexity of the circuit to be implemented into the FPGA students will be required to perform a hand design as well Sequential circuit design using state equations Several design methods are available for designing synchronous sequential circuits including the excitation table method design by state equations and design using the one hot method Since the D flip flop is an essential part of the FPGA we will focus on the state equation method which is well suited for D flip flops The general form of the state equation for a D flip flop is So the input for each D flip flop is simply determined by finding an expression for the next state for that flipQ t 1 D flop 1 Example Design a 4 bit counter using D flip flops and the state equation method A 4 bit counter also called a modulo 16 counter counts in the sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 and repeats The state diagram is shown in Figure 1 below 0 15 1 14 2 13 3 12 4 5 11 6 10 7 9 8 Figure 1 State diagram for a 4 bit counter The corresponding state table is shown in Figure 2 below Note that the state is shown in decimal form in the state diagram whereas it is shown in binary form in the state table with bit D as the MSB Present State Next State D C B A D C B A 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 Figure 2 State table for a 4 bit counter 2 The characteristic equation for a D flip flop is very simple Q t 1 D So the expression for the next state is simply connected to the D input on the flip flop Expressions for the next state for each of the four flip flops is determined using Karnaugh maps shown in Figure 3 below D t 1 C t 1 B t 1 1 01 1 0 0 1 1 0 1 11 1 0 0 1 1 0 1 10 1 0 0 1 01 0 1 1 0 1 11 0 0 1 0 10 0 01 1 1 1 0 1 11 1 1 1 1 10 0 10 1 0 1 0 11 1 1 0 1 0 0 0 1 01 0 0 1 0 0 1 0 0 0 10 10 10 10 11 11 11 11 01 01 01 01 A t 1 BA DC 00 00 1 BA DC 00 00 0 BA DC 00 00 0 BA DC 00 00 0 Figure 3 Karnaugh maps for the state equations for the 4 bit counter Minimal SOP expressions for each output yield the state equations shown below in Figure 4 D t 1 D C D B D A D C B A C t 1 C B C A C B A B t 1 B A B A A t 1 A Figure 4 State equations for the 4 bit counter The state equations above are implemented in the circuit shown below in Figure 5 D C D B D A D t 1 D C B A DD QD QD D MSB D C B C A C t 1 C B A B A DC QC QC C C Count DCBA B t 1 DD QB B B A QB A t 1 A B DA QA QA A A Clock Figure 5 Logic Diagram for the 4 bit counter E Preliminary Work 3 1 Draw the state diagram for the custom counter described below Each student should design an up down counter that will count out each of the unique digits 7 or below of his or her EmplID in the order in which they occur followed by the all digits from 0 to 7 that do not occur in the EmplID from highest to lowest Note that all counting sequences will have all eight digits The counter should include a count direction control X such that the counter will count in the manner described above when X 1 and in reverse order when X 0 An example is shown below Example EmplID 1468443 Counting sequence when X 1 1 4 6 3 7 5 2 0 Digits in your EmplID 7 or less in the order in which they occur Digits from 0 to 7 that are not in your EmplID from highest to lowest Counting sequence when X 0 0 2 5 7 3 6 4 1 i …