CMSC 411 Fall 2009 Homework 5 1 Cache performance Suppose we have a memory hierarchy with three levels of cache and also for simplicity suppose that all memory accesses are read accesses Assume that TL1 is the access time of level 1 cache TL2 is the access time of level 2 cache TL3 is the access time of level 3 cache TM is the access time of the main memory MRL1 is miss rate of level 1 cache MRL2 is miss rate of level 2 cache MRL3 is miss rate of level 3 cache a What is the average memory access time with three levels of cache as a function of these variables b What percentage of memory accesses will result in access to the main memory 2 Cache and virtual memory Suppose we have a cache with 128 blocks each containing 16 bytes of storage a If the cache uses direct mapping in which cache block would the byte with address 1011 1001 1000 1011 1010 1100 reside b If the cache uses set associative mapping with an index of length 4 bits in which set would the byte with address 1010 1001 1100 1011 0110 reside c Suppose that virtual addresses on this machine are 32 bits and that pages are 4KB each If the machine has 1MB of physical memory how many standard page table entries are required if all the pages are being used And what fraction of the pages can reside in memory at any point in time 3 Virtual memory Consider a Virtual Memory System with the following properties 48 bit virtual address space 32 bit physical address 4GB 16 Kbyte pages a What is the total size of the Page Table in bits for each process on this machine assuming that the Valid Protection Dirty and Use bits take a total of 4 bits and that all the virtual pages are being used b The Virtual Memory system is implemented with a two way set associative TLB with a total of 256 entries 128 sets Describe the Virtual Memory address organization i e how the address bits are partitioned for address translation and the process of mapping an address from the Virtual Memory space to the Physical Memory space 4 Multiprocessors H P problems 4 1 4 2
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