Administrivia Homework 3 due Thursday Read Appendix C of H P Wanli s office hours have changed CMSC 411 Computer Systems Architecture Lecture 12 Memory Hierarchy new one on class home page Alan Sussman als cs umd edu l d d CMSC 411 12 some from Patterson Sussman others Levels of the Memory Hierarchy Capacity A Access Ti Time Cost CPU Registers 100s Bytes 10s ns Cache K Bytes 10 100 ns 1 0 1 cents bit 1 0 1 t bit Main Memory M Bytes 200ns 500ns 200ns 0001 00001 cents bit Staging Xfer Unit Tape infinite sec min 10 8 faster Registers Instr Operands Blocks Temporal Locality Locality in Time If an item is referenced it will tend to be referenced again soon e g loops reuse Spatial Locality Locality in Space If an item is referenced items whose addresses are close by tend to be referenced soon e g straightline code e g code array access cache cntl 8 128 bytes Pages OS 512 4K bytes Files user operator Mbytes Last 15 20 years HW has relied on locality for to improve overall performance Disk CMSC 411 12 some from Patterson Sussman others The Principle of Locality Two Different Types of Locality Memory T Tape The Principle of Locality Program g accesses a relatively y small p portion of the address space p at any short period of time prog compiler 1 8 bytes Cache Disk G Bytes 10 ms 10 000 000 ns 6 5 10 10 cents bit Upper Level 2 Larger It is a property of programs that is exploited in machine design L Lower Level L l 3 CMSC 411 12 some from Patterson Sussman others 4 Programs with locality cache well Issues to consider Mem mory Addrress one e dot per a access B d locality Bad l lit behavior b h i Temporal Locality How big should the fastest memory cache memory be How do we decide what to put in cache memory If the cache is full how do we decide what to remove How do we find something in cache o do we e handle a d e writes tes How Spatial Locality Time Donald J Hatfield Jeanette Gerald Program Restructuring for Virtual Memory IBM Systems Journal 5 10 3 168 192 1971 CMSC 411 12 some from Patterson Sussman others First there is main memory CMSC 411 12 some from Patterson Sussman others 6 Then add a cache Jargon Jargon Each address of a memory location is partitioned into frame address which page block number which cache block contents the data block address tag index block offset Fig 5 5 Fig 55 CMSC 411 12 some from Patterson Sussman others 7 CMSC 411 12 some from Patterson Sussman others 8 How does cache memory work What is cache memory Main memory first The following slides discuss what cache memory is three organizations for cache memory direct mapped set associative fully associative how the bookkeeping is done Main memory is divided into cache blocks Each block contains many words 32 256 common now Important po ta t note ote All addresses add esses shown s o are a e in octal Addresses in the book are usually decimal 9 CMSC 411 12 some from Patterson Sussman others 10 CMSC 411 12 some from Patterson Sussman others Main memory Main memory cont Blocks are grouped into frames pages 3 frames in this picture Blocks are addressed by their frame number number and their block number within the frame 0 0 CMSC 411 12 some from Patterson Sussman others 11 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 0 1 1 1 2 1 1 1 3 4 5 CMSC 411 12 some from Patterson Sussman others 1 6 1 7 2 0 2 1 12 2 2 Cache memory cont Cache memory Cache has many MANY fewer bl k th blocks than main i memory eachh with ith a block number 0 1 2 3 4 5 6 Initially i i ll all ll the h valid bits bi set to zero 7 0 1 2 3 4 5 6 7 10 21 42 53 74 25 16 77 a memory address 10 21 42 53 74 25 16 77 data a valid bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a dirty bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 CMSC 411 12 some from Patterson Sussman others 14 CMSC 411 12 some from Patterson Sussman others Cache memory cont Where can a block be placed Block 12 placed in 8 block cache Fully F ll associative i ti direct di t mapped d 2 way 2 sett associative i ti Full Mapped Directt Mapped Di M d 12 mod 8 4 2 W Assoc 2 Way Ass 12 mod 4 0 01234567 01234567 01234567 Cache 1111111111222222222233 01234567890123456789012345678901 Memory CMSC 411 12 some from Patterson Sussman others 15 Suppose want to load block 14 octal from memory into cache cache 10 21 42 53 74 25 16 77 Three ways to organize cache h direct mapped set associative fully associative 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 CMSC 411 12 some from Patterson Sussman others 2 3 4 5 6 7 16 Direct mapped cache In direct mapped cache block 14 can only be put in the cache block with address 4 Direct mapped cache cont 0 1 2 3 4 5 6 7 After the load the contents look like this 0 1 2 3 4 5 6 7 10 21 42 53 74 25 16 77 10 21 42 53 14 25 16 77 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 So the cache will no longer hold the block with memory y address 74 17 CMSC 411 12 some from Patterson Sussman others Set associative cache Set associative cache cont Set 0 Set 1 Set 2 Set 3 Set 0 Set 1 Set 2 Set 3 In set associative cache each memory block can be put in any of a set of possible blocks in cache For example if divide cache into 4 sets block 14 can be put in any p y block in Set 0 since last two bits of 14 octal are zero 0 18 CMSC 411 12 some from Patterson Sussman others 1 2 3 4 5 6 7 10 24 41 55 72 26 13 77 So after loading the block cache memory might look like this this 0 1 2 3 4 5 6 7 14 24 41 55 72 26 13 77 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMSC 411 12 some from Patterson Sussman others 19 CMSC 411 12 some …
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