Computer Systems Architecture Final Exam Cheat Sheet Dec 17 2001 Professor Sam H Noh Fig 3 1 Fig 3 22 Figs 2 22 2 24 Fig 5 29 Fig 5 41 Operation of the Alpha AXP 21064 data TLB during address translation Fig 8 11 A write invalidate cache coherence protocol for a write back cache showing the states and state transitions for each block in the cache
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